Directional Etch for 3D NAND Memory Hole Alignment
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Solution Overview
Problem
The manufacturing of 3D NAND devices faces challenges in aligning memory holes due to photolithography overlay, dry etch tilt, and dry etch twist errors, leading to misalignment and increased complexity and cost with existing solutions.
Innovation Solution
A process flow that includes forming memory holes with an increased critical dimension in the upper portion and using a directional etch tool to create shoulder regions, followed by filling and planarization, which helps mitigate misalignment errors and maintains electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the upper critical dimension of memory holes is increased to overcome alignment challenges, then alignment margin is improved, but manufacturing complexity increases and bowing occurs leading to out-of-specification memory holes
Solution Approach 1:
The patent applies local quality by creating shoulder regions with enlarged critical dimension only in specific locations (upper portions of memory holes) rather than uniformly increasing the critical dimension throughout. This localized modification provides alignment margin where needed while maintaining normal dimensions in other areas, avoiding the bowing issues associated with uniform dimension increases.
2Manufacturing precision
If an inter-deck manufacturing flow is implemented between formation of each layer including lithography, dry etch, strip, fill, and CMP, then alignment precision is improved, but manufacturing cost and time increase and additional process errors are introduced
Solution Approach 1:
The patent applies preliminary action by forming the shoulder regions with enlarged critical dimension during the initial memory hole formation process, before the stacking and alignment operations occur. This pre-established feature provides built-in alignment margin that compensates for subsequent process variations, eliminating the need for additional inter-deck processing steps.
3Ease of manufacture
If conventional etching is used to form memory holes, then manufacturing simplicity is maintained, but misalignment errors occur due to photolithography overlay, dry etch tilt, and dry etch twist errors
Solution Approach 1:
The patent applies parameter changes by modifying the critical dimension parameter in specific regions to create shoulder regions with enlarged dimensions. This parameter modification provides a geometric feature that is tolerant to alignment errors, as the enlarged upper portion creates a larger target area that can accommodate photolithography overlay, dry etch tilt, and dry etch twist variations without causing misalignment failures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces misalignment errors and maintains electrical performance by providing a sufficient width in the sidewalls, preventing defects and improving manufacturing yield.
Implementation Method 1
dry etch tilt error; and lower deck memory hole 106d and upper deck memory hole 108d are misaligned due to a dry etch twist error
Data Source
AI summary
A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.