Carrier Manufacturing Process for Reduced Chip Package Thickness
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Solution Overview
Problem
Conventional chip package structures have a significant thickness due to the need for encapsulating bonding wires, which increases the risk of short circuits and limits circuit layout space.
Innovation Solution
A manufacturing process for a carrier that involves forming a first substrate with a circuit layer and contacts, applying a solder mask to expose the contacts, and bonding a second substrate with an opening to the first substrate, allowing direct electrical connection of chips to the contacts and reducing the thickness of the chip package structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires are used to electrically connect chips to contacts, then electrical connection is achieved, but the encapsulant height must be increased to prevent short circuits, resulting in increased chip package thickness
Solution Approach 1:
The patent extracts the bonding wires and encapsulant from the traditional connection method. Instead of using bonding wires that require encapsulation, the chip is directly connected to contacts through solder balls, eliminating the need for encapsulant and reducing package thickness while maintaining short circuit prevention through proper contact exposure in the opening.
Solution Approach 2:
The patent changes the connection approach from a three-dimensional wire bonding method requiring vertical encapsulation space to a planar direct connection method where contacts are exposed in an opening, allowing chips to be mounted directly on the substrate surface without requiring significant vertical space for encapsulant.
2Ease of manufacture
If a conventional substrate structure with all contacts on one surface is used, then manufacturing is simple, but circuit layout space is limited
Solution Approach 1:
The substrate is segmented into different functional regions: an opening area where contacts are exposed for direct chip connection, and other areas with standard circuit layers. This segmentation allows increased circuit layout space by providing dedicated contact areas while maintaining standard manufacturing processes for the remaining substrate regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases circuit layout space and reduces the thickness of the chip package structure by allowing chips to be electrically connected directly to the contacts within the opening, minimizing the risk of short circuits and enhancing manufacturing efficiency.
Implementation Method 1
a second substrate having a third surface, a fourth surface, and an opening configured within the second substrate extending from the third surface to the fourth surface is provided. The fourth surface of the second substrate is bonded to the first surface of the first substrate.
Data Source
AI summary
A manufacturing process of a carrier is disclosed. First, a first substrate is provided. A circuit layer having a number of contacts is formed on a surface of the first substrate. Then, a solder mask is formed on the circuit layer and exposes the contacts. Next, a second substrate having an opening is bonded to the surface of the first substrate to form a carrier, and the opening exposes the solder mask and the contacts of the first substrate. Since the contacts are located within the opening, a circuit layout space can be increased, and a chip disposed in the opening can be electrically connected to the contacts directly, so as to reduce the thickness of a chip package structure. Besides, the carrier is formed by laminating the first and the second substrates. Hence, the manufacturing process of the carrier is simplified and yield of the carrier is promoted.