Carrier Aggregation RFIC Using One PLL for Multi-Carrier Translation
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Solution Overview
Problem
Current RFIC designs require multiple phase-locked loops (PLLs) for carrier aggregation, leading to increased area occupation and high power consumption.
Innovation Solution
A radio-frequency integrated chip (RFIC) configured to use a single phase-locked loop (PLL) to support multiple carrier transmitters and receivers, with each carrier receiver or transmitter using a divided frequency signal for frequency translation, reducing the number of PLLs needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple individual PLLs are used for each carrier transmitter and receiver, then frequency stability and signal processing capability are improved, but chip area occupation and power consumption increase
Solution Approach 1:
Multiple PLLs are merged into a single shared PLL that serves all carrier transmitters and receivers. The patent implements a common PLL architecture where one PLL generates a reference frequency signal that is distributed to multiple frequency dividers, each associated with different carriers. This consolidation maintains frequency stability for all carriers while significantly reducing the total chip area occupied by PLL circuits.
Solution Approach 2:
The single PLL is designed to perform multiple functions by generating a universal reference frequency signal that can be divided and distributed to support multiple different carrier frequencies. The frequency dividers enable the same PLL output to serve different carriers with different frequency requirements, making the PLL system universal rather than dedicated to individual carriers.
2Reliability
If multiple individual PLLs are used for each carrier transmitter and receiver, then frequency stability is improved, but power consumption increases
Solution Approach 1:
Multiple power-consuming PLL units are merged into a single PLL, eliminating redundant power consumption from multiple identical circuits performing the same function. The single PLL consumes power once to generate the reference frequency, which is then freely distributed to multiple carriers without additional PLL power costs, significantly reducing total power consumption while maintaining frequency stability.
Solution Approach 2:
The single PLL provides universal frequency generation capability for all carriers, meaning one power source (the PLL) serves multiple functions (generating reference signals for multiple carriers). This multi-functionality eliminates the need for multiple separate power-consuming PLL units, reducing overall power consumption while maintaining the frequency stability required for reliable communication.
3Area of stationary object
If a single PLL is used for multiple carrier transmitters and receivers, then chip area and power consumption are reduced, but frequency translation complexity increases
Solution Approach 1:
Frequency dividers are introduced as intermediary components between the single PLL and the multiple carriers. The PLL generates a high-frequency reference signal, and the frequency dividers act as mediators to convert this single reference signal into multiple different frequency signals required by different carriers. This intermediary approach simplifies the overall architecture compared to using multiple PLLs while managing the frequency translation requirements.
Data Source
AI summary
Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for farther translating the frequencies of the receive signal in the digital domain.