Conductive Carrier-Tunneling Layer for Vertical LEDs
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Solution Overview
Problem
The challenge in manufacturing GaN thin films is the lack of a suitable substrate material with a matching lattice constant and thermal expansion coefficient, leading to stress issues and high resistivity, which prevents the formation of vertical LEDs with contacts on opposite sides of the substrate.
Innovation Solution
A semiconductor structure is developed with a conductive carrier-tunneling layer composed of alternating III-nitride layers with different bandgaps and thicknesses, eliminating the need for an AlN layer between the substrate and the superlattice, allowing for balanced stress and reduced resistivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If an AlN layer is used between the substrate and III-nitride layers to reduce thermal expansion stress, then stress compensation is improved, but resistivity increases and vertical LED formation is prevented
Solution Approach 1:
The patent changes the electrical parameter of the stress compensation layer by using thin III-nitride layers (2-10 nm) instead of thick AlN layers. This thickness reduction transforms the layer from insulating to conductive while maintaining stress compensation functionality through the same superlattice structure.
Solution Approach 2:
The patent creates a composite superlattice structure alternating between AlN and GaN layers. This composite approach combines the stress compensation capability of AlN with the electrical conductivity of GaN, achieving both functions simultaneously in a single integrated structure.
2Ease of manufacture
If silicon substrates are used for GaN growth due to cost and thermal conductivity, then manufacturing cost and heat dissipation are improved, but lattice mismatch causes stress and high resistivity
Solution Approach 1:
The patent segments the interface between silicon substrate and GaN layers into multiple thin alternating layers of AlN and GaN forming a superlattice. This segmentation creates intermediate steps that gradually bridge the lattice mismatch between silicon and GaN, reducing dislocation density and improving crystalline quality.
Solution Approach 2:
The AlN/GaN superlattice acts as an intermediary structure between the silicon substrate and the active GaN layers. This intermediate superlattice layer system mediates the lattice and thermal expansion coefficient mismatch, enabling high-quality GaN growth on silicon while maintaining electrical conductivity.
3Stress or pressure
If AlN layer thickness is increased to improve stress compensation, then stress reduction is improved, but electrical conductivity decreases and carrier tunneling is blocked
Solution Approach 1:
The patent changes the thickness parameter of the AlN layers to 2-10 nm, which is thin enough to allow quantum mechanical carrier tunneling while still providing sufficient stress compensation. This precise parameter control enables simultaneous achievement of mechanical and electrical performance.
Solution Approach 2:
The patent applies different thickness ratios of AlN and GaN layers locally within the superlattice structure. By optimizing the local thickness parameters of each layer type, the structure achieves stress compensation where needed while maintaining carrier tunneling pathways through the thinner AlN sections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the formation of vertical optoelectronic devices with reduced operation voltage and easier operation, as the conductive carrier-tunneling layer facilitates carrier tunneling and stress compensation without the need for discrete voltage values.
Implementation Method 1
a conductive carrier-tunneling layer over the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm
Implementation Method 2
The AlN layer has the function of reducing the stress caused by the difference in coefficients of thermal expansion (CTE) between the substrate and the overlying III-nitride layers
Data Source
AI summary
A semiconductor structure includes a substrate and a conductive carrier-tunneling layer over and contacting the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm; and second III-nitride layers having a second bandgap lower than the first bandgap, wherein the first III-nitride layers and the second III-nitride layers are stacked in an alternating pattern. The semiconductor structure is free from a III-nitride layer between the substrate and the conductive carrier-tunneling layer. The semiconductor structure further includes an active layer over the conductive carrier-tunneling layer.