Carrier Wafer Edge Etching to Eliminate Overhang Residue

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Solution Overview

Problem

During semiconductor device manufacturing, residual material from photoresists and other processing materials gets trapped in the overhang structure of the carrier wafer, leading to interference with subsequent processing operations and increased risk of device failure.

Innovation Solution

A method involving a trimming process on the non-bonding area of the device wafer, followed by thinning and a corona etching process, is employed to prevent or reduce the overhang structure, minimizing residual material and reducing the risk of interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the carrier wafer is used during processing operations on the backside of the substrate, then the semiconductor device can be supported and processed, but residual material from photoresists and other materials becomes trapped within an overhang in the carrier wafer

Engineering Contradiction:
Improvedevice failure riskVSAvoidresidual material trapping
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The method performs preliminary actions by applying photoresist removal treatment and conducting etching operations on the carrier wafer before the main processing operations on the substrate backside. This preliminary preparation prevents residual material from being trapped in the overhang structure during subsequent processing, thereby eliminating the harmful effect while maintaining device support functionality

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention converts the potentially harmful overhang structure that traps residual material into a beneficial feature by performing targeted etching operations. The etching process modifies the overhang structure to create a configuration that actually facilitates the removal of residual material, transforming the original problem into a solution that enhances processing effectiveness

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Object-generated harmful factors

If photoresist removal treatment is performed on the carrier wafer, then residual material is minimized, but additional processing steps are required

Engineering Contradiction:
Improveresidual materialVSAvoidprocessing steps
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The invention merges multiple processing operations into a unified approach. The photoresist removal treatment is combined with etching operations and carrier wafer preparation steps into an integrated process sequence. This consolidation achieves effective residual material removal while minimizing the total number of discrete processing steps by performing multiple functions in a coordinated manner

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the risk of device failure by minimizing residual material in the overhang structure, thereby enhancing production yield and ensuring smooth subsequent processing operations.

Implementation Method 1

performing an etching process on the non-bonding area of the carrier wafer

Methodology Applied
Scientific EffectCorona discharge: Corona Discharge

Data Source

PatentUS12568780B2Semiconductor device and method of manufacturing
Publication Date: 2026.03.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12568780B2 patent drawing
  • US12568780B2 patent drawing
  • US12568780B2 patent drawing

AI summary

A method of manufacturing a semiconductor device includes reducing a thickness of a device wafer bonded to a carrier wafer, wherein the device wafer includes a device, a portion of the carrier wafer beyond the device, in a plan view, is called a non-bonding area, and a portion of the carrier wafer overlapping the device, in the plan view, is called a device area. The method further includes performing an etching process on the non-bonding area of the carrier wafer, wherein the etching process is performed completely outside the device area of the carrier wafer.