Carrier Wafer Surface Shaping for Thickness-Uniform Polishing
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Solution Overview
Problem
Conventional substrate polishing methods often result in uneven thickness, causing substrates to fall out of tolerance due to differential polishing rates, leading to unusable substrates.
Innovation Solution
A method involving lapping and polishing of carrier wafers with differential pressure, speed, or time between the center and edge portions to create convex or concave shapes, followed by finish polishing to achieve a substantially flat surface, using a polishing apparatus with an adjustable weight and counterweight system to control force and shape.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional polishing methods are used on substrates, then the polishing process can be completed, but the substrate thickness becomes uneven and falls out of tolerance
Solution Approach 1:
The patent applies preliminary action by pre-shaping the carrier wafer surface into a convex or concave configuration before the final polishing step. This pre-shaping compensates for the expected differential polishing rates that will occur during subsequent polishing, ensuring that the substrate maintains uniform thickness and stays within tolerance specifications after polishing is complete.
Solution Approach 2:
The patent implements local quality by creating different surface configurations (convex or concave) in specific regions of the carrier wafer. The center and edge portions are deliberately given different curvatures to compensate for the fact that different regions will experience different polishing rates, thereby achieving uniform thickness across the entire substrate after polishing.
2Ease of operation
If differential polishing rates occur between center and edge portions, then polishing can proceed, but the substrate becomes unusable
Solution Approach 1:
The patent applies local quality by creating region-specific surface configurations on the carrier wafer. The center portion and edge portion are given different curvatures (convex or concave) to compensate for their inherently different polishing rates. This localized differentiation ensures that despite varying polishing speeds across the substrate, the final thickness remains uniform and the substrate remains usable.
Solution Approach 2:
The patent implements preliminary anti-action by pre-introducing curvature to the carrier wafer surface that opposes and compensates for the differential polishing rates. The convex or concave pre-shaping creates a counterbalancing effect that offsets the tendency for uneven thickness development during polishing, thereby preventing substrate rejection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that the carrier wafers can compensate for polishing-induced thickness variations, maintaining substrate tolerance and usability by achieving a flat surface post-polishing.
Implementation Method 1
lapping a first surface and a second surface of the carrier wafer such that the carrier wafer is substantially flat
Implementation Method 2
polishing the first surface of the carrier wafer with at least one of a differential pressure, a differential speed or a differential time between a center portion and an edge portion of the carrier wafer such that the first surface has a convex or concave shape
Data Source
AI summary
A method of forming a carrier wafer includes the steps of: lapping a first surface and a second surface of the carrier wafer such that the carrier wafer is substantially flat, the carrier wafer comprising a glass, glass-ceramic or ceramic material, wherein the carrier wafer has a diameter of from 250 mm to 450 mm and a thickness of from 0.5 mm to 2 mm after lapping; and polishing the first surface of the carrier wafer with at least one of a differential pressure, a differential speed or a differential time between a center portion and an edge portion of the carrier wafer such that the first surface has a convex or concave shape.


