Pipelined Zero Crossing Detector Using Carry Save Adders

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Solution Overview

Problem

Existing zero crossing detectors are too slow for high-speed applications due to significant horizontal carry propagation delay in their adder arrays, which limits their performance in clock recovery and other applications.

Innovation Solution

The use of carry save adders combined with fully pipelined logic in the adder array design substantially reduces horizontal carry propagation delay, enhancing the speed and efficiency of zero crossing detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional adder arrays are used in zero crossing detectors, then the device can perform addition operations, but horizontal carry propagation delay significantly reduces operating speed

Engineering Contradiction:

Improveoperating speedVSAvoidcarry propagation delay

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The adder array is segmented into multiple independent columns, where each column processes a specific bit position. Carry save adders are used to segment the carry propagation path, allowing multiple additions to occur in parallel without sequential carry dependency, thus reducing the overall carry propagation delay and increasing operating speed.

Inventive Principle:

Principle #1Segmentation

2Productivity

If more adder cells are used to increase processing capability, then the detector can handle more input signals, but chip area increases

Engineering Contradiction:

Improveprocessing capabilityVSAvoidchip area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

Multiple adder operations are merged into a single integrated adder array structure using carry save adders. This combining approach allows the circuit to process multiple input signals simultaneously through shared resources, increasing processing capability without proportionally increasing chip area, as the same hardware resources are reused across different processing stages.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS7424507B1High speed, low power, pipelined zero crossing detector that utilizes carry save adders

Publication Date: 2008.09.09 NAT SEMICON CORP

AI summary

A zero crossing detector employs carry save adders combined with fully pipelined logic to provide two-bit, three-bit or four-bit zero crossing detection. The detector offers the advantages of very high operating speed, very low power dissipation, low adder cell count and reduced chip area.