Computation Using Non-Contact Making Devices TRIZ Cases

Sign extension emulation reduces circuit area and fanout by replacing hardware bits with software-based partial product adjustments.

Segmented processor architecture merges functional units via a unified control unit to resolve communication bottlenecks in recurrent neural network operations.

A fast combinatorial algorithm rearranges calculations to minimize arithmetic operations.

A method scales quantized integers using bit-shift adjustments and integer multiplication factors.

Multiplier-accumulator circuitry transforms M×M matrices into N×N formats via Winograd logic, increasing throughput without proportional complexity.

Word-level operator-to-cell mapping reduces runtime and memory usage by segmenting the process into coarse word-level and fine bit-level stages.

A PIM normalizer circuit processes mantissa data using search and shift mechanisms to accelerate arithmetic operations within memory arrays.

Dynamic carry networks link reconfigurable logic blocks to resolve bit accuracy deterioration in accumulative operations while minimizing resource wastage.

A hardware circuit generates average pooling outputs by convolving input tensors with identity matrix kernels.

Redundant routing circuitry bypasses defective DSP blocks, stitching adjacent units to maintain complex operations despite manufacturing defects.

A Karatsuba-based multiply-accumulate circuit splits digital signals into portions processed by parallel multiplier and adder circuits.

Carry save adders combined with fully pipelined logic reduce horizontal carry propagation delay in zero crossing detectors, enabling high-speed operation.

A fused multiply-add apparatus dynamically selects computation paths based on operand values to optimize processing speed.

Converts index vectors to sparse tensors, enabling neural network accelerators to perform scatter operations without external CPU or GPU units.

Segmenting the adder into parallel stages with composite gates reduces circuit size while maintaining operation speed.

Radix-4 Booth encoding with parallel encoders reduces multiplication processing time by generating candidate partial products.

Segmented pipeline arithmetic logic unit reduces silicon area and processing time by applying pre-computed correction values to lookup tables.

Three-transistor bit comparators minimize capacitance and power consumption while maintaining noise margins through optimized pre-charging and discharging.

A computing in memory cell integrates semiconductor elements to perform matrix multiplication directly within the storage array.

Dual-rail photonic processors encode data in optical signal differences, reducing noise susceptibility and optical loss during matrix multiplication.

Reuse precomputed fine-grid flow solutions to optimize coarse grid permeability scaling, reducing computational time and cost.

Segmented upper, lower, and middle shift circuits resolve FMA processing speed bottlenecks by enabling parallel multi-precision operand alignment.

Segmenting workloads into specialized tensor engines resolves the performance versus energy efficiency trade-off in deep learning inference.

Compresses partial products using a Booth encoder and compression tree to generate corrected carry and sum outputs.

A method partitions numerators and converts denominators to leverage floating-point hardware for integer division.

Integrated circuit merges memory array and page buffer to eliminate data transfer bottlenecks between storage and processing units.

Bitmap extraction skips zero values to reduce processing energy during sparse matrix multiplication.

Parallel floor and ceiling calculation circuitry generates candidate values to remove residual sign determination from the critical path.

Segmented DSP blocks optimize the multiplier to adder ratio for FFT efficiency, reducing routing complexity compared to conventional 1:1 designs.