Reconfigurable Logic Blocks for Dynamic Carry Computation Networks
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Solution Overview
Problem
In semiconductor integrated circuits, accumulative addition and multiply-and-accumulation operations require large bit numbers, leading to bit accuracy deterioration when using processor elements with small bit numbers, and employing multiple processor elements to improve accuracy results in resource wastage and reduced efficiency.
Innovation Solution
A semiconductor integrated circuit design featuring reconfigurable logic blocks with dynamic networks for data and carry bit connections, allowing for efficient computation across varying bit widths and reducing resource wastage by utilizing processor elements for carry computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple processor elements are used to improve bit accuracy in accumulative operations, then bit accuracy is improved, but resource usage increases and efficiency decreases
Solution Approach 1:
The patent divides the computational task into two functional segments: first processor elements perform accumulative addition operations, while second processor elements专门 handle carry computation. This segmentation allows each element type to be optimized for its specific function, improving overall accuracy without requiring every element to perform all operations, thus maintaining efficiency.
Solution Approach 2:
The patent introduces a carry network as an intermediary component that connects first and second processor elements. This carry network efficiently transmits carry bits between stages, enabling accurate multi-bit computations without requiring direct connection between all processor elements, thereby maintaining system efficiency while improving precision.
2Measurement precision
If processor elements with large bit numbers are used, then bit accuracy in accumulative operations is improved, but device complexity increases
Solution Approach 1:
Instead of using single processor elements with large bit numbers, the patent segments the computation into multiple elements with smaller bit widths. First processor elements handle primary computation while second processor elements handle carry propagation, distributing the complexity across multiple simpler components rather than one complex element.
Solution Approach 2:
The patent designs processor elements with multi-functionality where first processor elements can perform both accumulative addition and carry generation, while second processor elements specialize in carry computation. This universal design allows flexible configuration to achieve high bit accuracy without requiring every element to be overly complex.
3Measurement precision
If normalization is performed for every computation to maintain bit accuracy, then bit accuracy is improved, but computational time increases
Solution Approach 1:
The patent performs preliminary carry computation using second processor elements before the final accumulation is complete. By preparing and propagating carry bits in advance through the carry network, the system avoids the need for time-consuming normalization operations after computation, maintaining both accuracy and speed.
Solution Approach 2:
The patent enables continuous carry propagation through the carry network during the computation process itself, rather than performing carry operations as separate post-processing steps. This continuous action integrates carry handling into the main computation flow, eliminating idle time and maintaining computational efficiency while ensuring accuracy.
Data Source
AI summary
There is provided a semiconductor integrated circuit including: a plurality of first logic blocks which are reconfigurable, the plurality of first logic blocks inputting data of a first bit width and performing computation; a first network connecting the plurality of first logic blocks in a dynamically reconfigurable manner; a plurality of second logic blocks inputting data of a second bit width different from the first bit width and performing computation; a second network connected to outputs of the plurality of second logic blocks; and a third network connecting a carry bit output of a computing unit included in the first logic block to an input of a computing unit included in the second logic block in a dynamically reconfigurable manner.