Fused Multiply-Add Apparatus Adaptive Computation
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Solution Overview
Problem
Conventional fused multiply-add (FMA) techniques perform unnecessary add and multiply operations even when they are not required, leading to inefficiencies in processing speed and power consumption, particularly in high-performance applications like wireless communication and 3D multimedia systems.
Innovation Solution
A FMA apparatus and method that divide floating-point numbers into n-bit segments, generate partial products, and use carry save and carry select adders to optimize the FMA operation by skipping unnecessary computations based on the mantissa of the third floating-point number, thereby reducing power consumption and improving processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional FMA methods always perform add and multiply operations, then the operation is complete according to IEEE 754 standard, but processing speed decreases and power consumption increases due to unnecessary operations
Solution Approach 1:
The patent applies dynamics by making the FMA operation adaptive rather than static. The apparatus dynamically selects between different operation paths (full FMA vs. simplified operations) based on the actual values of input operands. Specifically, when the third operand is zero, the system dynamically switches to perform only multiplication, and when the second operand is one, it performs only addition, thereby optimizing processing speed and power consumption while maintaining IEEE 754 compliance
Solution Approach 2:
The patent changes the operational parameters of the FMA unit based on input conditions. By detecting specific parameter values (such as zero or one in operands), the system adjusts the computation depth and operation type accordingly. This parameter-based adaptation allows the same hardware to efficiently handle different computational scenarios without always executing the complete FMA sequence
2Reliability
If conventional FMA methods always perform add and multiply operations, then the result is always accurate according to IEEE 754 standard, but power consumption increases due to unnecessary computations
Solution Approach 1:
The patent applies preliminary action by performing operand value detection before executing the main FMA computation. The apparatus checks whether the third operand equals zero or the second operand equals one prior to initiating multiply or add operations. This preliminary check enables the system to skip unnecessary computations, thereby reducing power consumption while ensuring that accurate operations are always performed when required by IEEE 754 standards
Data Source
AI summary
A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero.