Multi-precision Arithmetic Right Shift Circuit for FMA Units
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Solution Overview
Problem
Current processor architectures face challenges in efficiently performing fused multiply-add (FMA) operations on floating-point numbers, particularly in handling results with more significant bits than available mantissa bits, leading to inefficiencies in floating-point arithmetic processing.
Innovation Solution
The implementation of a method and device that utilize upper, lower, and middle shift circuits to perform arithmetic right shift operations, allowing for efficient handling of mantissa addition and rounding in FMA units by detecting shift conditions and providing selective inputs to the lower shift circuit, thereby improving the alignment and compression of operands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional single-shift-circuit architecture is used, then device complexity is reduced, but productivity and processing speed of FMA operations deteriorate due to inability to handle multi-precision arithmetic efficiently
Solution Approach 1:
The shift operation is divided into multiple independent shift circuits (upper shift circuit, lower shift circuit, and middle shift circuit) that operate in parallel on different segments of the operand. Each circuit handles a specific portion of the multi-precision arithmetic operation, allowing simultaneous processing and significantly improving FMA operation throughput.
Solution Approach 2:
The patent transitions from a single-dimensional sequential shift approach to a multi-dimensional parallel architecture. By introducing multiple shift circuits operating on different bit-width segments (e.g., 54-bit, 27-bit, 18-bit operands) simultaneously, the system adds a spatial dimension to the shift operation, enabling concurrent processing of multiple arithmetic operations.
2Measurement precision
If multi-precision arithmetic is implemented with multiple shift circuits, then processing precision and productivity improve, but device complexity increases due to additional circuits and control logic
Solution Approach 1:
The multi-precision operand is segmented into multiple fixed-width portions (e.g., 54-bit upper, 27-bit middle, 18-bit lower) that are processed by dedicated shift circuits. This segmentation maintains precise control over each bit-width segment while enabling parallel processing, thus improving arithmetic precision without requiring a single complex monolithic circuit.
Solution Approach 2:
The system dynamically adjusts shift amounts and operand widths as parameters to match different FMA operation requirements. By changing the shift circuit parameters (shift count, operand segmentation) rather than the fundamental architecture, the system achieves high precision for various precision requirements while maintaining relatively simple circuit designs.
3Adaptability or versatility
If fixed shift amount is used, then control logic is simplified, but adaptability deteriorates when handling variable precision requirements in FMA operations
Solution Approach 1:
The shift circuits are designed with dynamic control capabilities where shift amounts and operand selections can be adjusted based on the specific FMA operation requirements. The system dynamically determines which shift circuit to use and what shift amount to apply, allowing adaptation to variable precision needs while maintaining efficient parallel processing architecture.
Solution Approach 2:
Multiple shift circuits are designed with universal functionality to handle different operand widths and shift amounts through common control logic. Each shift circuit can process various bit-width operands (e.g., 54-bit, 27-bit, 18-bit) by receiving appropriate control signals, making the overall system highly adaptable to different FMA precision requirements without requiring separate dedicated circuits for each case.
Data Source
AI summary
A method includes receiving, by each of an upper shift circuit and a lower shift circuit, an operand for an arithmetic right shift operation. The upper shift circuit is configured to provide an upper output, the lower shift circuit is configured to provide a lower output, and the upper output concatenated with the lower output is a result of the arithmetic right shift operation. The method also includes receiving a shift value for the arithmetic right shift operation; responsive to the shift value, detecting a shift condition in which a portion of, but not all of, the operand could be shifted into bits corresponding to the lower output; and responsive to detecting the shift condition, providing, by a middle shift circuit, at least a portion of the operand to the lower shift circuit as a selectable input.