Karatsuba Digital Multiply-Accumulate Circuit for Low Power AI
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Solution Overview
Problem
Existing digital signal multiplication techniques in artificial neural networks are inefficient, consuming high power and occupying large chip areas, especially in machine learning and AI applications where fast and efficient multiply-accumulate operations are crucial.
Innovation Solution
The implementation of a circuit based on the Karatsuba algorithm, which splits digital signals into portions and uses multiple multiplier and adder circuits to perform multiplication and addition operations, reducing the number of required multipliers and enhancing processing speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional digital signal multiplication techniques are used in artificial neural networks, then the multiplication operations can be performed, but the power consumption is high and the chip area occupied is large
Solution Approach 1:
The patent applies segmentation by dividing digital signals into portions (e.g., most significant bits and least significant bits) and processing them separately through multiple multiplier circuits. This allows the use of smaller, more efficient multiplier circuits that consume less power while maintaining multiplication accuracy through subsequent addition operations that combine the partial products.
2Area of stationary object
If traditional digital signal multiplication techniques are used in artificial neural networks, then the multiplication operations can be performed, but the chip area occupied is large
Solution Approach 1:
The patent divides the multiplication operation into segments processed by multiple smaller multiplier circuits rather than one large multiplier. This segmentation reduces the total chip area required while maintaining multiplication speed through parallel processing of signal portions.
Solution Approach 2:
The patent merges the results from multiple smaller multiplier circuits through addition circuits to produce the final multiplication result. This combining approach allows the system to achieve the functionality of a large multiplier using smaller, more area-efficient components.
3Productivity
If the Karatsuba algorithm is implemented with multiple multiplier and adder circuits, then the processing speed is enhanced, but the device complexity increases
Solution Approach 1:
The Karatsuba algorithm in the patent segments the multiplication process into operations on signal portions, enabling faster parallel processing. The increased complexity is managed by organizing these segmented operations into a structured circuit architecture with dedicated multiplier and adder circuits for each segment.
Solution Approach 2:
The patent transforms the traditional single-path multiplication process into a multi-dimensional parallel processing structure by simultaneously processing multiple signal portions through different multiplier circuits. This dimensional expansion increases processing speed while the modular nature of the architecture helps manage the resulting complexity.
Data Source
AI summary
Certain aspects provide methods and apparatus for multiplication of digital signals. In accordance with certain aspects, a multiplication circuit may be used to multiply a portion of a first digital input signal with a portion of a second digital input signal via a first multiplier circuit to generate a first multiplication signal, and multiply another portion of the first digital input signal with another portion of the second digital input signal via a second multiplier circuit to generate a second multiplication signal. A third multiplier circuit and multiple adder circuits may be used to generate an output of the multiplication circuit based on the first and second multiplication signals.