Multiplication Circuitry Sign Extension Emulation

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Solution Overview

Problem

Existing multiplication circuitry in processors faces challenges in achieving efficient processing performance and energy efficiency, particularly when handling signed multiplication operations and sign extensions, which increase circuit area and fanout, leading to performance limitations.

Innovation Solution

The proposed multiplication circuitry includes a plurality of adder sub-arrays with independent enable control signals, a result assembly adder array, and sign extension emulation techniques. These techniques apply default zero extension and adjust partial products to emulate sign extension, reducing the need for traditional sign extension bits and minimizing fanout.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional sign extension bits are used in multiplication circuitry, then signed multiplication accuracy is maintained, but circuit area and fanout increase leading to performance limitations

Engineering Contradiction:

Improvesigned multiplication accuracyVSAvoidcircuit area and fanout

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts the sign extension function from traditional hardware circuitry and relocates it to software handling. The multiplication circuit performs unsigned multiplication without dedicated sign extension bits, and the sign extension is applied by software based on the sign bit of the result, thereby reducing circuit area and fanout while maintaining accuracy.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical/hardware sign extension mechanism with a software-based solution. Instead of using hardware circuits to automatically extend sign bits, the system uses software instructions to detect the sign bit and perform appropriate extension, substituting physical circuit complexity with algorithmic processing.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Adaptability or versatility

If multiple adder sub-arrays are used to support different data element sizes, then versatility is improved, but device complexity and energy consumption increase

Engineering Contradiction:

Improvedata element size supportVSAvoidnumber of adder sub-arrays

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces dynamic control signals that enable or disable specific adder sub-arrays based on the required data element size. This dynamic configuration allows the same physical hardware to adapt to different multiplication sizes (e.g., 8x8, 16x16, 32x32 bits) by activating only the necessary sub-arrays, reducing both complexity and energy consumption for smaller operations.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent segments the multiplication circuitry into multiple independent adder sub-arrays, each capable of handling specific data element sizes. This segmentation allows selective activation of sub-arrays based on operational requirements, providing versatility while managing complexity through modular design.

Inventive Principle:

Principle #1Segmentation

3Productivity

If all adder sub-arrays are always enabled to support maximum data element size, then processing capability is maintained, but energy efficiency deteriorates

Engineering Contradiction:

Improvemaximum multiplication capabilityVSAvoidenergy consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent uses dynamic enable/disable control signals to activate only the necessary adder sub-arrays based on the actual data element size being processed. When smaller multiplications are performed, only the corresponding smaller sub-arrays are enabled, significantly reducing energy consumption while maintaining the capability to handle maximum-size operations when needed.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent applies partial action by enabling only the minimum necessary adder sub-arrays required for the current operation size. Instead of always activating all sub-arrays, the system activates exactly what is needed (partial action), avoiding the energy waste of running unnecessary circuitry while preserving full capability when required.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS20250028504A1Multiplication circuitry, system, chip-containing product, and computer-readable medium

Publication Date: 2025.01.23 ARM LTD

AI summary

Multiplication circuitry comprises adder sub-arrays which each add partial products derived from first/second operands. Sub-array result values generated by the adder sub-arrays are added in a result assembly addition to generate at least one multiplication result value representing a result of signed multiplication of the first operand and the second operand. Sign extension emulation is performed for a sign-extension-emulated sub-array result value added in the result assembly addition, by applying a default zero extension to the sign-extension-emulated sub-array result value regardless of its sign and emulating an effect of sign extending the sign-extension-emulated sub-array result value using another of the assembled values. Another example of multiplication circuitry applies default zero extension to a third signed operand being added to a product of first/second signed operands, and emulates sign extension of the third signed operand by adjusting one of the partial products derived from the first/second signed operands.