PIM Normalizer Circuit for MAC Operator Data Processing
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Solution Overview
Problem
Deep learning neural networks require increased computational resources and data communication between memory and processor, leading to performance degradation due to the separation of these components in traditional hardware systems.
Innovation Solution
A PIM (Processing-In-Memory) device integrates processor and memory on a semiconductor chip, utilizing a MAC operator with a normalizer that includes a '0' search circuit, '1' search circuit, selector, exponent adder, and mantissa shifter to enhance data processing speed within the neural network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of layers in neural network is increased to improve AI performance, then computational performance is improved, but the amount of computation required increases exponentially
Solution Approach 1:
The patent merges memory and processor into a single PIM device, allowing arithmetic operations to be performed directly within the memory array. This integration eliminates the need for separate computation units and reduces the exponential growth of computational requirements by performing operations in-place during data access.
Solution Approach 2:
The normalizer circuit acts as an intermediary component within the PIM device that performs normalization operations on accumulated data. This mediator handles critical computational tasks (normalization) internally, reducing the burden on external processing units and mitigating the exponential computation growth.
2Device complexity
If general hardware system with separated memory and processor is used, then system architecture is simple, but data communication between memory and processor limits AI performance
Solution Approach 1:
The patent combines memory and processor functions into a single PIM device, eliminating the separation between these components. This merger allows arithmetic operations to be performed directly within the memory array, removing the performance bottleneck caused by data communication between separate memory and processor units.
3Speed
If PIM device is used to integrate processor and memory, then data processing speed is improved, but device complexity increases
Solution Approach 1:
The PIM device is segmented into distinct functional units: MAC operators for arithmetic operations, normalizer circuits for normalization, and memory arrays for data storage. This segmentation allows each component to be optimized independently while working together to achieve high-speed processing, managing the complexity through modular design.
Solution Approach 2:
The PIM device is designed as a multi-functional unit that simultaneously performs memory access and arithmetic operations. The MAC operators can perform multiplication and accumulation while the normalizer circuits perform normalization, allowing the device to handle multiple computational tasks within a single integrated architecture, improving speed without proportionally increasing complexity.
Data Source
AI summary
A normalizer includes a “0” search circuit configured to search for a position of a most significant “0” bit of first mantissa data included in input data to output first search data, a “1” search circuit configured to search for a position of a most significant “1” bit of the first mantissa data included in the input data to output second search data, a selector configured to output one selected by a bit value of first sign data of the input data between the first search data and the second search data, as selected data, an exponent adder configured to add first exponent data included in the input data and the selected data to output second exponent data included in output data, and a mantissa shifter configured to perform a shifting operation on the first mantissa data, based on the selected data to output second mantissa data included in the output data.