Multiplier-Accumulator Circuitry for Matrix Processing Pipelines
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Solution Overview
Problem
Existing multiplier-accumulator circuitry struggles to efficiently process and transform input data and weights from M × M to N × N matrices, which limits data throughput and processing efficiency in applications like image processing.
Innovation Solution
The integration of Winograd type processes and Z-to-Y conversion logic circuitry within the multiplier-accumulator circuitry allows for the transformation of input data and weights from M × M to N × N matrices, enhancing data throughput and processing efficiency by implementing multiple execution pipelines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional multiplier-accumulator circuitry is used to process M×M matrices, then the circuit structure is simple, but the data throughput and processing efficiency are limited
Solution Approach 1:
The circuit is divided into multiple execution pipelines (first, second, third, and fourth pipelines) that operate in parallel. Each pipeline processes specific portions of the N×N matrix operations, allowing simultaneous computation of multiple elements. This segmentation enables the circuit to handle larger matrices and increases data throughput by distributing the computational load across multiple independent processing units.
Solution Approach 2:
The circuit transforms the processing from M×M matrix operations to N×N matrix operations (where N > M), effectively changing the dimensional capacity of the processor. By implementing pipelines that can simultaneously compute multiple N×N matrix elements, the circuit operates in a higher-dimensional computational space, thereby increasing throughput without proportionally increasing overall complexity.
2Productivity
If multiple execution pipelines are implemented to process N×N matrices, then processing efficiency increases, but the device complexity increases
Solution Approach 1:
Each execution pipeline is designed with universal functionality to perform multiple operations including multiplication, accumulation, and transformation of N×N matrix elements. The pipelines use shared computational resources and standardized processing stages, allowing them to handle different portions of the matrix computation using the same architectural blueprint. This multi-functionality reduces the incremental complexity added by each additional pipeline compared to having specialized circuits for each operation.
3Productivity
If Winograd type processes are implemented for data transformation, then data throughput increases, but the computational complexity of transformation operations increases
Solution Approach 1:
The Winograd transformation operations are performed as preliminary steps before the main multiplication and accumulation operations. The circuit includes dedicated transformation stages that pre-process the N×N matrix elements according to Winograd algorithms, transforming the input data into a form that enables more efficient subsequent processing. By performing these transformations upfront in the pipeline architecture, the circuit prepares the data for high-speed parallel computation, increasing overall throughput despite the added transformation complexity.
Data Source
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Figure 2A
AI summary
An integrated circuit including memory to store image data and filter weights, and a plurality of multiply-accumulator execution pipelines, each multiply-accumulator execution pipeline coupled to the memory to receive (i) image data and (ii) filter weights, wherein each multiply-accumulator execution pipeline processes the image data, using associated filter weights, via a plurality of multiply and accumulate operations. In one embodiment, the multiply-accumulator circuitry of each multiply-accumulator execution pipeline, in operation, receives a different set of image data, each set including a plurality of image data, and, using filter weights associated with the received set of image data, processes the set of image data associated therewith, via performing a plurality of multiply and accumulate operations concurrently with the multiply-accumulator circuitry of the other multiply-accumulator execution pipelines, to generate output data. Each set of image data includes all of the image that correlates to the output data generated therefrom.