Computing in Memory Cell for AI Matrix Multiplication
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Solution Overview
Problem
Artificial intelligence networks, such as deep neural networks, require matrix multiplication operations that involve significant data movement from memory to computing circuits, leading to high energy consumption and processing time.
Innovation Solution
A computing in memory (CIM) cell design that incorporates semiconductor elements and memory cell circuits to perform matrix multiplication operations directly within the memory, reducing the need for data movement by using computing word-lines and bit-lines to control semiconductor elements for in-memory computing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If data is moved from memory to computing circuits for matrix multiplication, then computing operations can be performed, but energy consumption and processing time increase
Solution Approach 1:
The patent merges memory and computing functions into a single integrated structure where memory cells directly perform computing operations. The memory cell circuit includes storage elements for holding data and semiconductor elements configured to perform multiplication operations, eliminating the need for separate computing circuits and reducing data movement between memory and processor.
Solution Approach 2:
The memory cell is designed with multi-functionality, serving both as storage and computing units. The same memory cell structure that stores data also performs multiplication operations through its semiconductor elements, allowing it to fulfill multiple roles within the computing system.
2Power
If data is moved from memory to computing circuits for matrix multiplication, then computing operations can be performed, but processing time increases
Solution Approach 1:
The integration of memory and computing functions within the same cell structure eliminates data transfer time between separate memory and processing units. The memory cell directly performs multiplication operations on stored data, significantly reducing the time required for computing operations.
3Productivity
If computing operations are performed outside memory, then data can be processed, but the number of data movements increases
Solution Approach 1:
The patent combines memory storage and computing operations within the same physical structure, allowing data to be processed in-place without movement to external computing circuits. This integration dramatically reduces the number of data movement operations required.
4Quantity of substance
If traditional memory architecture is used, then data storage is achieved, but computing power is limited due to data movement requirements
Solution Approach 1:
The memory cell is designed with multi-functionality, serving both as storage and computing units. The same memory cell structure that stores data also performs multiplication operations through its semiconductor elements, allowing it to fulfill multiple roles within the computing system.
Solution Approach 2:
The patent merges memory and computing functions into a single integrated structure where memory cells directly perform computing operations. The memory cell circuit includes storage elements for holding data and semiconductor elements configured to perform multiplication operations, eliminating the need for separate computing circuits and reducing data movement between memory and processor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient in-memory computing, reducing energy consumption and processing time by performing matrix multiplication operations within the memory cell array, thereby minimizing data movement and enhancing computing power.
Implementation Method 1
A control terminal of the first semiconductor element is adapted to be coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. The operation of the first semiconductor element and the second semiconductor element is equivalent to a multiplication operation performed on the first data bit and the second data bit.
Implementation Method 2
The fourth semiconductor element is configured to selectively provide a weight resistance corresponding to a weight. A first terminal of the fourth semiconductor element is adapted to be coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is adapted to be coupled to a second computing bit-line.
Data Source
AI summary
A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.