Partial Product Compression for Fused Multiply-Accumulate Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing arithmetic processing devices face challenges in efficiently and accurately executing fused multiply-and-accumulate instructions with packed-single-precision floating-point operands, leading to increased cycle delay and power consumption.
Innovation Solution
The implementation of a method and apparatus that compresses partial products during the fused multiply-and-accumulate operation, utilizing a Booth encoder, carry-save adders, and a compression tree to generate corrected carry and sum outputs, allowing for the execution of fused multiply-and-accumulate instructions with packed single-precision operands, thereby reducing cycle delay and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional separate multiply and add instructions are used, then implementation simplicity is maintained, but computation speed and accuracy deteriorate due to multiple rounding steps
Solution Approach 1:
The patent combines the multiply and add operations into a single fused multiply-and-accumulate (FMAC) instruction that computes the entire sum C+A×B to full precision before rounding, eliminating the need for separate multiply and add instructions and their associated multiple rounding steps
2Productivity
If packed single-precision format is used, then data processing efficiency is improved, but computation accuracy deteriorates due to precision limitations
Solution Approach 1:
The patent processes packed single-precision operands by dividing them into high and low parts, computing their contributions separately in different precision dimensions, then combining the results to achieve both efficiency and accuracy
3Reliability
If high-part result computation waits for low-part result, then computation accuracy is maintained, but cycle delay increases
Solution Approach 1:
The patent performs preliminary computation of the high-part result using available information before the low-part result is ready, then applies corrections after the low-part result becomes available, eliminating the need to wait for low-part completion before starting high-part computation
4Device complexity
If conventional compression tree is used, then device complexity is reduced, but power consumption and cycle delay increase
Solution Approach 1:
The patent segments the compression tree into multiple levels with selective activation, where different compression levels are enabled or disabled based on operand characteristics, reducing unnecessary computation and power consumption while maintaining accuracy
Data Source
AI summary
The disclosed embodiments relate to methods and apparatus for accurately, efficiently and quickly executing a fused multiply-and-accumulate instruction with respect to floating-point operands that have packed-single-precision format. The disclosed embodiments can speed up computation of a high-part of a result during a fused multiply-and-accumulate operation so that cycle delay can be reduced and so that power consumption can be reduced.