Carry Save Array Multiplier for Dual Arithmetic Operations
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Solution Overview
Problem
Conventional processors require dedicated circuitry for arithmetic operations, leading to increased cost and complexity, especially for multiply and accumulate (MAC) instructions, which are not optimized for performance and cost balance.
Innovation Solution
A processor design incorporating a carry save array multiplier with cascaded partial product generators and sequencing logic that can perform both multiplication and addition, eliminating the need for a dedicated adder for double precision results, thereby reducing circuit area and cost while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated circuitry is provided for arithmetic operations including separate adder and multiplier, then arithmetic functionality and reliability are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The carry save array multiplier is designed to perform both multiplication and addition operations using the same hardware circuitry. The multiplier can be configured to execute multiplication when control signals indicate multiply operations, and addition when control signals indicate add operations, eliminating the need for separate dedicated adder and multiplier circuits while maintaining full arithmetic functionality
Solution Approach 2:
The patent combines the functions of separate adder and multiplier circuits into a single carry save array multiplier unit. By merging these previously distinct arithmetic operations into one unified hardware structure, the overall device complexity and component count are reduced while preserving all necessary arithmetic capabilities
2Manufacturing precision
If separate adder circuitry is provided for double precision results, then manufacturing precision is improved, but device complexity and area increase
Solution Approach 1:
The carry save array multiplier serves dual purposes by handling both single-precision multiplication and double-precision addition operations. When double precision results are required, the same multiplier circuitry is utilized to perform the necessary addition operations, eliminating the need for separate dedicated adder circuitry and thereby reducing the overall circuit area while maintaining double precision accuracy
3Productivity
If conventional hardware multiplier design is used, then arithmetic performance is improved, but device complexity and cost increase
Solution Approach 1:
The multiplier circuit incorporates dynamic control mechanisms that allow it to adapt its operation mode based on the required arithmetic function. Control signals dynamically configure the carry save array to perform either multiplication or addition, enabling the circuit to maintain high arithmetic performance for different operations while using a single reconfigurable structure rather than multiple static dedicated circuits
Data Source
AI summary
A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.