Computations Using Contact-Making Devices TRIZ Cases

Multiple pulse generators and combiners split a UWB chaotic signal into frequency channels so users can communicate simultaneously with low RF complexity.

Biasing transistors sense low-frequency IM2 products to cancel even-order distortion, improving IIP2 and receiver sensitivity without calibration.

Unpredictable branches in JPEG 2000 MQ decoding are replaced with table-driven arithmetic to speed decoding on general-purpose processors.

Resynchronized phase clocks and lower-impedance routing improve mixer phase accuracy, boosting image rejection and SNR in RF receivers.

Floating-gate current-mode circuits execute large-scale tensor operations in parallel, cutting neural network power use and computation time.

Operand collectors and parallel dot products cut repeated register-file loads, speeding matrix multiply-accumulate execution.

Analog memory arrays feed an output block that converts column currents into digital bits.

This case uses double-precision or 48-bit MAD hardware to replace emulation for wide integer multiplication workloads.

A metastability-containing sorting circuit uses parallel prefix computation to sort inputs across clock domains.

A floating-point multiplier generates an overflow mask by right shifting a predetermined pattern to extract overflow values before significand shifting.

A floating-point operand normalization circuit converts denormal inputs to normalized form before division.

Cascaded partial product generators in a carry save array multiplier perform multiplication and addition to reduce circuit area.

Three concurrent calculations resolve exponent differences and leading zeros, reducing operation time without increasing adder width requirements.

An alignment shifter combines partial products in a carry-save adder to optimize hardware usage.

A multiply-add pipeline bypasses unrounded intermediate results to input operands for immediate use in subsequent operations.

A processing-in-memory device integrates multiplication-and-accumulation circuits directly within memory regions to execute arithmetic operations.

Integrated systolic delay circuitry within DSP blocks reduces addition time and enables faster clock speeds for finite-impulse-response filtering.

A multi-bit accumulator uses 1-bit Wallace trees and tristate buffers to perform add operations on single-bit input data.

Polyphase reactive circuitry creates a high-Q impedance peak at the RF input, eliminating separate SAW filters to improve receiver selectivity.

Winograd transformations reduce multiplication operations in fast filtering, lowering processing time and boosting efficiency on FPGAs.

A weight normalizer circuit distributes expected sums into normalized weights using iterative bit shifts and additions.

A modular multiplier apparatus predicts long path carry using medium calculation results to accelerate arithmetic operations.

Accumulating operator segments input data into matched exponents and compensation values to prevent mantissa distortion during addition.

A dispatch mechanism uses a user command block to move instructions between host and co-processors via cache coherency.

Pre-distortion circuits generate correction signals to cancel harmonic and image distortions, improving SFDR and ACLR in multi-channel communication systems.

A square cell power detector uses bipolar transistors and offset voltage elements to generate output current proportional to input voltage squared.

Prediction circuitry generates shift indications to pre-normalize operand significands before addition in a unified floating point adder unit.

A magnetoresistance mixer uses a perpendicular magnetic field and impedance circuit to generate multiplication signals.

Dedicated coefficient storage unit eliminates floating point load instruction overhead and reduces pipeline pressure during Taylor series calculations.

A normalized integer divider reuses floating-point hardware to compute quotient digits via maximum digit count logic.

Trailing zeros counting circuitry generates suffix values for mantissa concatenation, eliminating multibit OR operations that increase processing latency.

A compensation signal generator offsets input signals to enable efficient artificial neural network operations.

Speculative multiply-add recoding forces zero addends to reuse the floating-point adder normalization circuit.

A chemically amplified positive resist composition combines a specific base resin with an alkali-soluble polymer to enable high-sensitivity pattern formation.

An extra transistor diverts tail current in a multi-tanh cell to extend the linear input range without increasing the noise floor.

A floating-point multiplier uses early injection rounding circuitry to generate product significands directly from partial products.

A fast floating point half-adder architecture applies operands immediately to datapaths without early condition detection.

An AC-coupled differential driver circuit filters DC bias voltage through a low pass filter to enable independent DC potential adjustment at the modulator common node.

Capacitor-based component separation eliminates external filters, reducing device complexity while maintaining multiband capability.

A division unit with a normalization circuit and multiple divide engines processes operands concurrently.

Segmented parallel amplifier paths maintain linearity while resolving the trade-off between spectral efficiency and power consumption.

A multiply-and-accumulate circuit counts product occurrences to generate partial sums, reducing hardware complexity.

A conditional calculator performs cryptographic operations using left-shifting or multiplication to secure intermediate values.