Floating-Point Multiplier Early Overflow Detection

Solution Overview

Problem

Existing data processing apparatuses face challenges in efficiently performing floating-point multiplication, especially when handling non-normalized input operands, as they require conversion to normalized representation and struggle with early overflow detection in both normal and subnormal input scenarios.

Innovation Solution

The apparatus employs partial product generation, adder, exponent calculation, shift, mask generation, and comparison circuitry to generate and format the product significand, allowing early overflow detection by using a right-shifted overflow mask before shifting the product significand, and parallel left and right shift circuitry to enhance processing speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the floating-point multiplier operates quickly and efficiently, then processing speed is improved, but the construction complexity increases due to additional input stage capability required to convert non-normalised inputs

Engineering Contradiction:

Improveprocessing speedVSAvoidconstruction complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing normalization shift amounts in a lookup table before the actual multiplication operation. This allows the multiplier to quickly determine the required normalization shift for non-normalized inputs without performing complex real-time calculations, thereby improving processing speed while managing construction complexity through pre-computation

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary normalization stage that converts non-normalized inputs into a standardized format before multiplication. This intermediary component handles the complexity of input conversion separately, allowing the main multiplier to operate efficiently on normalized data while the normalization logic is managed by dedicated circuitry

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If additional capability is provided in input stages to convert non-normalised inputs into normalised representation, then flexibility is improved, but device complexity increases

Engineering Contradiction:

Improveinput flexibilityVSAvoidinput stage complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary normalization stage that converts non-normalized inputs into a standardized format before multiplication. This intermediary component handles the complexity of input conversion separately, allowing the main multiplier to operate efficiently on normalized data while the normalization logic is managed by dedicated circuitry

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies preliminary action by pre-calculating and storing normalization shift amounts in a lookup table before the actual multiplication operation. This allows the multiplier to quickly determine the required normalization shift for non-normalized inputs without performing complex real-time calculations, thereby improving processing speed while managing construction complexity through pre-computation

Inventive Principle:

Principle #10Preliminary action

3Productivity

If overflow detection is performed after shifting the product significand, then processing simplicity is maintained, but processing time increases due to sequential operation

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidprocessing time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating the overflow mask based on the determined shift amount before the actual shifting operation occurs. This allows the overflow detection to be performed in parallel with the shifting operation rather than sequentially, eliminating the time penalty while maintaining processing simplicity

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent uses a predetermined mask pattern that covers all possible overflow positions and applies it to the product significand. By using an excessive mask that covers more positions than strictly necessary, the system can detect overflow in parallel with shifting without requiring complex conditional logic, thus improving productivity while minimizing time loss

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS9836279B2Apparatus and method for floating-point multiplication

Publication Date: 2017.12.05 ARM LTD

AI summary

An apparatus and method for floating-point multiplication are provided. Two partial products are generated from two operand significands, which are then added to generate a product significand. The value of an unbiased result exponent is determined from the operand exponent values and leading zero counts, and a shift amount and direction for the product significand are determined in dependence on a predetermined minimum exponent value of a predetermined canonical format. The product significand is shifted by the shift amount in the shift direction. An overflow mask identifying an overflow bit position of the product significand is generated by right shifting a predetermined mask pattern by the shift amount, and the overflow mask is applied to the product significand to extract an overflow value at the overflow bit position. This extraction of the overflow value happens before the shift circuitry shifts the product significand, allowing an overall faster floating-point multiplication to be performed.