Floating-Point Adder Latency Reduction via Trailing Zeros Counting
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Solution Overview
Problem
Existing floating point adders face latency issues due to the need for explicit calculation of sticky bits during floating point addition and subtraction, which increases processing latency and reduces clock frequency.
Innovation Solution
The solution involves indirectly calculating a bit equivalent to the sticky bit by determining the carry out from a sum dependent on the count of trailing zeros and exponent differences, using suffix values concatenated with the mantissa values, thereby reducing latency by performing this calculation in parallel with the right shift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a logical OR operation is performed on all bits shifted out of the significance range to determine the sticky bit, then the sticky bit is accurately determined, but the processing latency increases due to the multibit operation
Solution Approach 1:
The patent extracts only the necessary information from the shifted-out bits by counting trailing zeros instead of processing all bits through a multibit OR operation. This selective approach retrieves the sticky bit value without the latency penalty of examining every bit position.
Solution Approach 2:
The trailing zeros counting circuit operates in parallel with the mantissa alignment shift operation, performing the sticky bit determination beforehand. This preliminary action eliminates the sequential dependency that would otherwise cause latency in the addition process.
2Loss of time
If the trailing zeros counting circuit operates in parallel with the right shift operation, then latency is reduced, but the circuit complexity increases
Solution Approach 1:
The patent segments the sticky bit determination function into a dedicated trailing zeros counting circuit that operates independently and in parallel with the shift operation. This segmentation allows each component to be optimized for its specific function while reducing overall latency.
Solution Approach 2:
The trailing zeros counting circuit acts as an intermediary between the shifted-out bits and the sticky bit generation. It processes the trailing zero count and combines it with the exponent difference to produce the suffix values, serving as a mediator that enables parallel operation without excessive complexity.
Data Source
AI summary
Floating point adder circuitry 16, 18, 20 is provided with far-path circuitry 18 and near-path circuitry 20. The far-path circuitry utilises a count of trailing zeros TZ and a difference in the input operand exponents to form respective suffix values which are concatenated with the mantissas of the input addends and serve when summed to generate a carry out taking the place of a conventionally calculated sticky bit. Within the near-path, minimum value circuitry 46 is used to calculate the lower of a leading zeros count of the intermediate mantissa produced in a subtraction and the larger of the input operand exponent values such that a left shift applied to the intermediate mantissa value is not able to produce a invalid floating point result due to applying a left shift to remove leading zeros that is too larger and accordingly corresponds to an exponent which cannot be validly represented.