Metastability-Containing Sorting Circuits via Parallel Prefix Computation
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Solution Overview
Problem
Existing digital circuits face challenges in efficiently sorting inputs across clock domains due to metastability, which can lead to errors and require significant time for reliability, and existing sorting networks are not optimized for size and speed while handling metastable inputs.
Innovation Solution
The development of CMOS-based metastability-containing (MC) sorting circuits that utilize Kleene logic and parallel prefix computation to reduce depth and size, while maintaining constant fan-out and minimizing errors, by decomposing comparisons into four-valued operations and using Gray code for encoding, allowing for efficient sorting of metastable inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional synchronizers are used to resolve metastability, then reliability is improved, but time delay increases
Solution Approach 1:
The patent converts the harmful effect of metastability into a useful property by treating metastable states as valid input values in a four-valued logic system. Instead of trying to eliminate metastability through time-consuming synchronizers, the circuit accepts metastable inputs and propagates them through the sorting network, allowing the harmful phenomenon to be harnessed for functional operation.
Solution Approach 2:
The patent changes the logical parameter space from traditional binary logic to four-valued logic, where inputs can be stable 0, stable 1, or two metastable states. This parameter expansion allows the circuit to handle metastable inputs directly without requiring additional time for resolution, fundamentally changing how the system processes uncertain states.
2Speed
If sorting networks are optimized for speed, then depth is reduced, but size increases
Solution Approach 1:
The patent segments the sorting problem into manageable components by using the parallel prefix computation framework, which divides the sorting network into modular 2-sort elements arranged in a specific hierarchical structure. This segmentation allows for systematic optimization of the depth-size tradeoff while maintaining correctness.
Solution Approach 2:
The patent applies the parallel prefix computation technique, which uses a tree-based hierarchical structure to reduce the depth of the sorting network. By organizing 2-sort elements in a tree-like pattern rather than a linear sequence, the circuit achieves logarithmic depth while keeping the overall size manageable through shared subcomputations.
3Device complexity
If fan-out is increased to reduce circuit size, then device complexity decreases, but reliability deteriorates
Solution Approach 1:
The patent applies local quality optimization by carefully managing fan-out constraints in different regions of the circuit. Instead of uniformly limiting or allowing high fan-out throughout, the design selectively controls signal distribution to maintain reliability where metastability propagation is critical while achieving size efficiency where appropriate.
Data Source
AI summary
In order to provide smaller, faster and less error-prone circuits for sorting possibly metastable inputs, a novel sorting circuit is provided. According to the invention, the circuit is metastability-containing.