Octave-Range CMOS Power Mixer Array for Watt-Level Efficiency
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Solution Overview
Problem
Current power amplifiers face challenges in achieving high efficiency and linearity, especially in wideband watt-level power amplification, due to limitations in amplitude dynamic range, phase shift, and inefficiencies in DC-DC converters and digital implementations, which result in poor power efficiency and increased area requirements.
Innovation Solution
A monolithic power mixer array with a substrate, power generation units, a power combiner, and a digital controller that selectively operates power generation units based on modulation constellations like 2N-QAM and π/4-OQPSK, utilizing baseband analog replica linearizers and distributors to maintain linearity and efficiency, and an output transformer for impedance transformation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If linear power amplifiers are used to transmit non-constant envelope modulation schemes, then spectral efficiency is improved, but power efficiency deteriorates
Solution Approach 1:
The power amplifier is divided into multiple parallel amplification paths (e.g., multiple PAs with different power levels). Each path processes a portion of the signal, allowing the system to achieve high spectral efficiency through linear operation while improving overall power efficiency by selectively activating only the necessary number of amplifier paths based on signal requirements.
2Use of energy by moving object
If separate processing of amplitude and phase information is implemented, then system efficiency is improved, but device complexity increases
Solution Approach 1:
The patent combines amplitude and phase processing into a unified polar modulation architecture where the signal is represented in polar coordinates (amplitude and phase components). This allows separate processing of amplitude (via supply modulation) and phase (via baseband modulation) while integrating them in a single amplifier structure, thereby improving system efficiency without proportionally increasing device complexity.
3Measurement precision
If DC-DC converters are used for supply modulation, then amplitude information reconstruction is improved, but chip area increases
Solution Approach 1:
The patent extracts the inductor component from the chip by using an external inductor for the DC-DC converter. This removes the large area requirement for on-chip inductors while maintaining the amplitude reconstruction capability, thereby reducing chip area without sacrificing the precision of amplitude information reconstruction.
4Power
If digitally modulated polar power amplifiers are implemented, then lower power level performance is improved, but implementation in wideband watt-level setting becomes difficult
Solution Approach 1:
The patent implements a dynamic architecture where the number of active amplifier paths and their operating modes can be dynamically adjusted based on the required output power and bandwidth. This allows the system to operate efficiently at lower power levels using digital polar modulation while also adapting to wideband watt-level applications by activating additional paths and adjusting modulation parameters in real-time.
5Measurement precision
If high resolution RF-digital-to-analog converters are used, then conversion precision is improved, but layout area increases
Solution Approach 1:
The patent segments the digital-to-analog conversion function across multiple parallel amplifier paths rather than using a single high-resolution converter. Each path uses a lower-resolution converter, and the combined output achieves the required precision. This segmentation reduces the layout area of individual converters while maintaining overall conversion precision through the parallel architecture.
Data Source
AI summary
Power mixer arrays for providing watt-level power in mobile systems. In one embodiment, a fully-integrated octave-range CMOS power mixer that occupies only 2.6 mm2 using a 130 nm semiconductor process has been demonstrated. The power mixer provides an output power of +31.5 dBm into an external 50 Ω load with a power added efficiency (PAE) of 44% at 1.8 GHz and a full power gain compression of only 0.4 dB.