Integer Divider Using Floating-Point Hardware and NDQ Normalization

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Solution Overview

Problem

Existing integer division methods in microprocessors are inefficient, particularly for high-demand applications, as they often require separate floating-point and integer dividers, leading to increased die real estate and reduced performance.

Innovation Solution

The method involves normalizing the integer divisor and dividend to determine the maximum possible number of quotient digits (NDQ), allowing for efficient integer division using existing floating-point dividers, such as the Prabhu/Zyner algorithm, which reduces the number of cycles required for division.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate floating-point and integer dividers are provided, then both division operations can be performed, but die real estate increases

Engineering Contradiction:

Improvedivision operation capabilityVSAvoiddie real estate

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent makes the floating-point divider capable of performing both floating-point division and integer division by adding control logic that detects integer operands and switches the division algorithm accordingly. The same hardware resources (divider circuit, adders, shifters) are reused for both operation types, eliminating the need for a separate integer divider and reducing die area while maintaining full functionality for both division types

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Area of stationary object

If basic single bit per cycle (radix-2) integer divider is provided, then die real estate is reduced, but performance decreases

Engineering Contradiction:

Improvedie real estateVSAvoidinteger division performance

Core Design Contradiction:

Area of stationary objectVSProductivity

Solution Approach 1:

The patent dynamically adjusts the division algorithm and radix based on the input operands. When integer division is detected, the system can switch between different radix modes (radix-2, radix-4, radix-8) depending on the specific computational requirements and operand characteristics. This dynamic adaptation allows the floating-point divider hardware to achieve integer division performance comparable to or exceeding dedicated radix-2 integer dividers while maintaining space efficiency

Inventive Principle:

Principle #15Dynamics

3Productivity

If subtractive algorithms with fixed cycle sequences are used, then division is performed, but cycles are wasted when dividend is smaller than divisor

Engineering Contradiction:

Improvedivision operation completionVSAvoiddivision cycles

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent performs preliminary comparison of the dividend and divisor before initiating the full division sequence. By detecting early whether the dividend is smaller than the divisor (or will result in a quotient of zero), the system can terminate the division operation immediately after a single comparison cycle rather than executing the complete sequence of shift-subtract-compare operations. This preliminary check prevents wasted cycles and significantly reduces latency for cases where the result is zero or trivial

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS7539720B2Low latency integer divider and integration with floating point divider and method

Publication Date: 2009.05.26 ORACLE AMERICAN INC

AI summary

A method and device divides a dividend by a divisor, the dividend and the divisor both being integers. The method and device determine a maximum possible number of quotient digits (NDQ) based on a number of significant digits of the divisor and the dividend, normalizes the dividend and divisor, and calculates NDQ number of quotient digits from the normalized divisor and dividend.