Division Unit With Normalization Circuit And Multiple Divide Engines
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Solution Overview
Problem
High latencies in executing divide and square root instructions in processors due to their complexity, which negatively impact processor performance despite their low occurrence in most applications.
Innovation Solution
An integrated circuit with a division unit that includes multiple divide engines and a normalization circuit to normalize operands, along with a scheduler unit that manages instruction issuance to prevent collisions and optimize execution, allowing for parallel execution of multiple divide instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single divide engine is used to execute divide instructions, then the device complexity is reduced, but the execution latency increases significantly
Solution Approach 1:
The division unit is segmented into multiple divide engines (first divide engine, second divide engine, etc.) that can execute divide instructions in parallel. Each divide engine is a functional subset capable of independent operation, allowing simultaneous processing of multiple instructions and thereby reducing overall execution latency without requiring a completely complex redesign of the division unit
2Loss of time
If multiple divide engines are used to execute divide instructions in parallel, then the execution latency is reduced, but the device complexity increases
Solution Approach 1:
Multiple divide engines are merged into a single division unit that shares common resources including the normalization circuit, post-engine, and arbitration unit. This merging approach allows parallel execution capability while avoiding the full complexity of completely independent divide engines, as shared resources reduce the total component count and interconnections required
Solution Approach 2:
The normalization circuit and post-engine are designed as universal resources that can serve multiple divide engines. The normalization circuit normalizes operands for any divide engine, and the post-engine processes results from any engine, creating a multi-functional architecture that reduces overall device complexity while maintaining parallel execution capability
3Measurement precision
If a normalization circuit is added to normalize operands before division, then the execution accuracy is improved, but the device complexity increases
Solution Approach 1:
The normalization circuit performs preliminary normalization of dividend and divisor operands before they are passed to the divide engines. By preparing the operands in advance (shifting and exponent adjustment), the division operation itself can proceed more accurately and efficiently, improving execution precision while the normalization is handled as a preparatory step rather than an interruptive process
4Productivity
If a scheduler unit with counter management is implemented to manage instruction issuance, then the productivity is improved, but the device complexity increases
Solution Approach 1:
The scheduler unit uses counters (first counter, second counter) that provide feedback about the current execution state and resource availability. The scheduler monitors counter values and adjusts instruction issuance accordingly, creating a feedback-controlled system that optimizes throughput by dynamically adapting to the current state of the division unit without requiring complex external control logic
Data Source
AI summary
Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes a division unit that, in turn, includes a normalization circuit and a plurality of divide engines. The normalization circuit is configured to normalize a set of operands. Each divide engine is configured to operate on a respective normalized set of operands received from the normalization circuit. In some embodiments, the integrated circuit includes a scheduler unit configured to select instructions for issuance to a plurality of execution units including the division unit. The scheduler unit is further configured to maintain a counter indicative of a number of instructions currently being operated on by the division unit, and to determine, based on the counter whether to schedule subsequent instructions for issuance to the division unit.