Multi-tanh Multiplier Dynamic Tail Current Linearity

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing four-quadrant multipliers based on common-emitter multi-tanh transistor cells have a limited linear input range, which restricts their operational effectiveness at higher input signal levels due to increased nonlinearity and noise floor issues, and scaling down inputs to maintain linearity introduces transistor mismatch and noise problems.

Innovation Solution

Incorporating an extra transistor coupled to the common emitter node to dynamically divert and redirect tail current, allowing for increased compliance and extending the linear input range without increasing the noise floor, and using additional series-connected junctions and dual multipliers with feedback arrangements to enhance linearity and dynamic range.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the input signal level is increased to improve signal strength, then the output signal strength is improved, but the linearity of the multiplier deteriorates due to increased nonlinearity

Engineering Contradiction:
Improveoutput signal strengthVSAvoidlinearity
Core Design Contradiction:
PowerVSManufacturing precision

Solution Approach 1:

The patent applies dynamics by making the tail current dynamic rather than fixed. The tail current is adjusted based on the input signal level, allowing the multiplier to maintain linearity across a wider input range. The dynamic tail current compensation mechanism adapts the bias current to counteract nonlinear effects that occur at higher signal levels, thus resolving the contradiction between output signal strength and linearity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of tail current from a fixed value to a variable parameter that can be adjusted. By modifying the tail current parameter dynamically in response to input signal conditions, the multiplier maintains optimal linearity characteristics even when processing larger input signals, thereby resolving the contradiction between signal strength and linearity.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If the input signal is scaled down to maintain linearity, then the linearity is preserved, but the noise floor becomes more significant and transistor mismatch issues increase

Engineering Contradiction:
ImprovelinearityVSAvoidnoise floor
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The dynamic tail current adjustment allows the system to maintain linearity without requiring signal scaling. By adaptively changing the tail current parameter, the multiplier can process larger signals while maintaining linearity, thus avoiding the noise floor problems that would result from scaling down the input signal.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If a fixed tail current is used to simplify the circuit, then the circuit complexity is reduced, but the linear input range is limited

Engineering Contradiction:
Improvecircuit complexityVSAvoidlinear input range
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent introduces dynamic tail current adjustment while maintaining relatively simple circuit implementation. The dynamic compensation mechanism extends the linear input range without requiring complex circuitry, thus resolving the contradiction between circuit simplicity and adaptability to different signal levels.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7795948B2Super-symmetric multiplier
Publication Date: 2010.09.14 ANALOG DEVICES INC
  • US7795948B2 patent drawing
  • US7795948B2 patent drawing
  • US7795948B2 patent drawing

AI summary

A circuit includes a multi-tanh cell having a common-emitter node to receive a bias current, and an extra transistor coupled to the common-emitter node to dynamically divert a portion of the bias current from the multi-tanh cell. The circuit may be arranged as a multiplier with an input network arranged to apply two or more input signals to the multi-tanh cell. A second multi-tanh cell with an extra transistor may be arranged in a feedback loop where the outputs of the first and second multi-tanh cells are coupled together at an integrating node. A buffer drives the final output and feedback cell to cancel nonlinearities in the multiplier cells.