Floating Point Half-Adder Architecture Eliminating Operand Adjustment Delays
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Solution Overview
Problem
Existing floating point adder architectures that implement half-adder instructions require additional cycles and increased computation time, compromising the performance of floating point units by necessitating early detection of operand conditions and adjustments before execution.
Innovation Solution
A fast floating point half-adder architecture that eliminates the need for early detection of half-adder conditions, allowing operands to be immediately applied to datapaths, thereby executing half-adder instructions without delaying the presentation of operands to the pipelines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If early detection and adjustment of operand conditions is performed, then correct half-adder operation is achieved, but computation time increases and performance decreases
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing adjusted mantissa values (Am and Bm/2) in lookup tables before execution. When a half-adder operation is detected, the pre-computed values are immediately retrieved and used, eliminating the need for real-time adjustment during the critical computation path. This resolves the contradiction by performing the necessary adjustment work in advance rather than during execution.
Solution Approach 2:
The patent segments the computation process by separating the half-adder adjustment logic from the main addition pipeline. The adjustment operation is divided into independent lookup table retrievals that can be performed in parallel with the main addition operation, rather than sequentially. This segmentation allows the correctness requirement to be met while avoiding time loss in the critical path.
2Reliability
If early detection and adjustment of operand conditions is performed, then correct half-adder operation is achieved, but device complexity increases
Solution Approach 1:
The patent uses copying by creating pre-computed copies of the adjusted mantissa values (Am and Bm/2) in lookup tables. Instead of implementing complex real-time adjustment logic, the system creates static copies of all possible adjusted values and retrieves them during operation. This reduces device complexity by replacing dynamic adjustment circuitry with simple lookup and selection logic.
Solution Approach 2:
The adjustment values are pre-computed and stored in lookup tables during device fabrication or initialization, rather than computing them during operation. This preliminary action transfers the computational complexity from the operational phase to the setup phase, simplifying the operational device architecture while ensuring correctness.
3Reliability
If operands are delayed for condition detection and adjustment, then correct operation is ensured, but productivity decreases
Solution Approach 1:
The patent maintains continuity of useful action by allowing the main addition operation to proceed uninterrupted while the half-adder adjustment values are retrieved from lookup tables in parallel. The useful computation continues without delay, and the adjustment is applied continuously rather than interrupting the flow. This ensures both operational correctness and high productivity by eliminating sequential dependencies.
Solution Approach 2:
By pre-computing and storing adjustment values before execution, the system eliminates the need to delay operands for real-time adjustment. The preliminary preparation of adjustment data allows the main computation pipeline to maintain full speed while correctness is ensured through the pre-prepared values.
Data Source
AI summary
Apparatus and methods are disclosed for a floating point adder having half-adder capability that does not have the overhead of determining half-adder conditions prior to starting the SED, LED, and EXP datapaths.