Clock-Resynchronized Mixer Layout for Better Image Rejection
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Solution Overview
Problem
Current RF receiver systems face limitations in image signal rejection due to phase clock accuracy issues, particularly in high-frequency applications like satellite radio, where the attenuation of IF bandpass filters is insufficient, leading to reduced signal-to-noise ratio (SNR) and increased distortion.
Innovation Solution
The design incorporates a phase clock generator, latch, and multiplier with conductors of varying impedance to improve phase clock accuracy by resynchronizing phase clock signals and reducing signal routing length and loading mismatches, thereby enhancing image rejection in mixers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional conductor routing is used in mixers, then device complexity is reduced, but phase clock accuracy deteriorates due to unequal loading and routing length mismatches
Solution Approach 1:
The patent introduces a buffer circuit as an intermediary element between the phase clock generator and the mixing circuitry. This buffer circuit acts as a mediator that equalizes the loading conditions on different phase clock signal paths, thereby improving phase clock accuracy without requiring complex conductor routing adjustments throughout the entire mixer design.
2Measurement precision
If conductor routing length is reduced, then phase clock accuracy improves, but signal transmission losses increase
Solution Approach 1:
The patent modifies the electrical parameters of the conductor routing by adjusting conductor width, thickness, or material properties to change the impedance characteristics. This allows for shorter conductor lengths to be used while maintaining adequate signal transmission levels, thereby improving phase clock accuracy without excessive transmission losses.
3Object-affected harmful factors
If unequal loading on phase clocks is reduced, then image rejection improves, but device complexity increases due to additional matching components
Solution Approach 1:
The buffer circuit serves as an intermediary that equalizes the loading conditions on phase clock signals without requiring additional phase matching components throughout the signal path. By centralizing the loading equalization function in the buffer, the patent achieves improved image rejection while minimizing the increase in overall device complexity.
4Measurement precision
If phase clock signals are resynchronized, then signal-to-noise ratio improves, but additional circuitry is required
Solution Approach 1:
The patent combines the resynchronization function with the existing buffer circuit that is already required for impedance matching and loading equalization. By merging multiple functions (resynchronization, buffering, and loading equalization) into a single circuit element, the patent achieves improved signal-to-noise ratio without proportionally increasing device complexity.
Data Source
AI summary
A mixer (114) includes a phase clock generator (404), a latch (420), and a multiplier (118). The phase clock generator (404) provides a plurality of phase clock signals. The latch (420) is coupled to the phase clock generator (404) via a first plurality of conductors (410) and provides a plurality of resynchronized phase clock signals. The multiplier (118) is coupled to the latch (420) via a second plurality of conductors (430) and mixes an input signal using the plurality of resynchronized phase clock signals to provide a mixed output signal. The second plurality of conductors (430) is characterized as having a lower end-to-end impedance than an end-to-end impedance of the first plurality of conductors (410).