Current-Mode Tensor Circuits With Floating-Gate Reconfigurability
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Solution Overview
Problem
Existing digital neural network devices face challenges in efficiently executing large-scale transistor tensor operations due to high computational requirements, power consumption, and inflexibility, limiting their ability to perform complex neural network computations at a lower cost and energy consumption.
Innovation Solution
The use of floating-gate transistors with field-programmable threshold voltages to implement current-mode computation cells and summation circuits, allowing for parallel execution of transistor tensor operations, including matrix-vector and tensor contractions, while being configurable for multiple levels of neural network computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If digital neural network devices use traditional digital computation circuits, then they can execute neural network operations, but they consume high power and have long computational time
Solution Approach 1:
The patent replaces traditional digital computation circuits with current-mode computation circuits based on floating-gate transistors. This substitution uses analog current-mode operations instead of digital voltage-level logic, enabling parallel computation of tensor operations and significantly reducing both power consumption and computational time while maintaining computational accuracy.
Solution Approach 2:
The patent changes the operating parameters of the computation circuits by using floating-gate transistors with field-programmable threshold voltages. This allows the circuits to operate in current-mode with analog values representing tensor elements, enabling efficient parallel computation and reducing the time and energy required for neural network operations compared to traditional digital circuits.
2Adaptability or versatility
If digital neural network devices use fixed-architecture computation circuits, then they can execute specific neural network operations, but they lack flexibility for reconfiguration
Solution Approach 1:
The patent implements a universal current-mode computation circuit architecture using floating-gate transistors that can be configured to perform multiple types of neural network operations including matrix-vector multiplication, tensor contractions, and various activation functions. The field-programmable threshold voltages allow the same hardware to adapt to different computational tasks without requiring separate dedicated circuits for each operation type.
Solution Approach 2:
The patent introduces dynamic reconfigurability through field-programmable threshold voltages in floating-gate transistors. This allows the computation circuits to change their operational characteristics and connectivity patterns dynamically, enabling the same hardware architecture to be reconfigured for different neural network layers and operations, thus providing adaptability without proportionally increasing hardware complexity.
3Productivity
If digital neural network devices execute large-scale tensor operations, then they achieve high computational throughput, but they consume excessive power and time
Solution Approach 1:
The patent replaces sequential digital computation with parallel current-mode computation using floating-gate transistors. This substitution enables simultaneous execution of multiple tensor operations through analog current summation, dramatically increasing computational throughput while reducing the time required to complete large-scale neural network computations.
Solution Approach 2:
The patent implements continuous current-mode computation that maintains useful action throughout the computation process. The analog currents representing tensor elements flow continuously through the computation circuit, allowing parallel accumulation of results without the discrete switching and resetting required in digital circuits, thereby reducing computational time while maintaining high throughput.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces computational time and power consumption, enabling faster and more efficient execution of neural network operations, comparable to or surpassing the performance of GPUs and TPUs, with the added flexibility of reconfigurable hardware.
Implementation Method 1
floating-gate transistors with field-programmable threshold voltages
Data Source
AI summary
An integrated circuit includes a plurality of current-mode computation (CMC) branches, each including a plurality of CMC cells and a branch summation line. An individual CMC cell includes at least one computation transistor that produces a CMC output current that is a function of a channel current of the computation transistor. A branch summation line receives CMC cell output currents produced by a plurality of CMC cells, and produces a branch output current that is a current-mode summation of all received CMC cell output currents. A layer-one current summation circuit receives the branch output current produced by at least one branch summation line, and produces a layer-one current summation circuit output current that is a function of the received branch output currents. The layer-one current summation circuit may be field-programmable. In operation, the integrated circuit can perform transistor tensor operations by programming one or more layer-one current summation circuits to combine all branch output currents received by those layer-one current summation circuits. Using embodiments of the present invention, millions, billions, trillions or more of the CMC cells can be field-programmed to execute computations in parallel to support transistor tensor operations.