Floating-Point Operand Normalization Circuit for Denormal Division
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Solution Overview
Problem
Current processor implementations require software intervention for floating-point division with denormal operands, leading to increased execution cycles due to lack of hardware support for such operations.
Innovation Solution
A floating-point circuit with a normalization circuit and divide engine that normalizes denormal operands and determines the maximum possible number of digits in the quotient, allowing for iterative generation of the quotient directly in hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware support is restricted to normalized operands only, then the divide engine can operate efficiently with standardized inputs, but it cannot process denormal operands without software intervention, increasing execution cycles
Solution Approach 1:
The normalization circuit performs preliminary normalization of denormal operands before they reach the divide engine. By detecting denormal inputs and normalizing them in advance using left shift operations on the significand and adjusting the exponent accordingly, the circuit ensures that the divide engine always receives normalized operands, maintaining its efficient operation while expanding support to denormal inputs.
Solution Approach 2:
The normalization circuit acts as an intermediary between the input operands and the divide engine. It receives both normalized and denormal operands, processes them to produce normalized outputs, and passes these to the divide engine. This intermediary layer protects the divide engine from handling denormal cases directly while still enabling denormal input support.
2Reliability
If software traps are used to handle denormal operands, then correct division results can be obtained, but substantial extra execution cycles are required
Solution Approach 1:
The patent replaces the software-based trap mechanism with a hardware-based normalization circuit. Instead of transferring control to software routines that handle denormal operands through complex sequences of instructions, the normalization circuit performs the necessary normalization operations directly in hardware using shift and add circuits, dramatically reducing the time required to process denormal operands while ensuring correct results.
3Adaptability or versatility
If the divide engine processes denormal operands directly, then hardware support for denormal inputs is achieved, but the complexity of the divide engine increases significantly
Solution Approach 1:
The patent segments the division system into two distinct functional blocks: a normalization circuit that handles all denormal-to-normal conversion, and a divide engine that specializes in processing normalized operands. This segmentation allows each component to be optimized for its specific function, preventing the divide engine from becoming complex while still supporting denormal inputs through the dedicated normalization stage.
Solution Approach 2:
The normalization functionality is extracted from the divide engine and placed in a separate preprocessing circuit. By removing the complexity of denormal handling from the divide engine, the engine itself remains relatively simple and efficient, while the extracted normalization circuit handles all denormal operand processing independently before inputs reach the divide engine.
Data Source
AI summary
A floating-point circuit may include a floating-point operand normalization circuit configured to receive input floating-point operands of a given floating-point divide operation, the operands comprising a dividend and a divisor, as well as a divide engine coupled to the normalization circuit. In response to determining that one or more of the input floating-point operands is a denormal number, the operand normalization circuit may be further configured to normalize the one or more of the input floating-point operands and output a normalized dividend and normalized divisor to the divide engine, and dependent upon respective numbers of leading zeros of the dividend and divisor prior to normalization, generate a value indicative of a maximum possible number of digits of a quotient (NDQ). The divide engine may be configured to iteratively generate NDQ digits of a floating-point quotient from the normalized dividend and the normalized divisor provided by the floating-point operand normalization circuit.