Floating Point Adder with Prediction Circuitry for Fused Multiply Accumulate
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Solution Overview
Problem
The existing floating point adder units face performance issues due to the need for separate near and far paths, which complicates the execution of fused multiply accumulate operations and requires additional pipeline stages for rounding, especially when handling unrounded multiplication results.
Innovation Solution
The proposed solution involves prediction circuitry to generate a shift indication for pre-normalizing the significands of operands, detection of leading bit cancellation conditions, and the use of shared addition circuitry with result pre-normalization to perform additions efficiently, eliminating the need for separate near and far paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate near and far paths are used for floating point addition, then normalization accuracy is improved, but device complexity increases and execution time increases due to additional pipeline stages
Solution Approach 1:
The patent merges the separate near path and far path into a single unified adder unit. The selection between different addition modes (near path or far path) is dynamically controlled by a selector based on the relationship between input exponents, eliminating the need for physically separate processing paths while maintaining the accuracy benefits of both approaches.
Solution Approach 2:
The patent introduces dynamic control logic that determines at runtime whether to apply near path or far path processing based on the exponent relationship of the inputs. This dynamic selection allows the system to adapt to different input conditions without requiring static separate paths for each case, reducing overall device complexity while preserving normalization accuracy.
2Measurement precision
If separate near and far paths are used for floating point addition, then normalization accuracy is improved, but execution time increases due to additional pipeline stages
Solution Approach 1:
The dynamic selection mechanism allows the system to choose the faster near path when applicable (when exponents differ by at most 1) and only use the far path when necessary. This reduces the average execution time compared to always using the far path, while still maintaining normalization accuracy through selective application of the appropriate processing mode.
Solution Approach 2:
The patent applies different processing qualities locally based on input characteristics: the near path is used for cases requiring less processing (exponent difference ≤ 1), while the far path is used for cases requiring more processing (exponent difference > 1). This localized application of different processing modes optimizes execution time while maintaining accuracy where needed.
3Measurement precision
If FMA operations are performed using a separate adder unit, then multiplication accuracy is improved, but productivity decreases due to longer execution time
Solution Approach 1:
The patent makes the adder unit universal by enabling it to handle both standard floating point addition and FMA operations through the same processing path. The unrounded multiplication result is fed directly into the adder unit, which processes it using the same near/far path selection logic, eliminating the need for a dedicated FMA unit and improving throughput while maintaining accuracy.
Solution Approach 2:
The patent merges the FMA operation into the standard addition pipeline by feeding the unrounded multiplication result directly into the adder unit. This combines the multiplication and addition operations into a single unified processing flow, improving productivity by eliminating the need for separate FMA hardware while preserving multiplication accuracy through the use of unrounded results.
Data Source
AI summary
An apparatus and method are provided for performing an addition operation on operands A and B in order to produce a result R, the operands A and B and the result R being floating point values each having a significand and an exponent. The apparatus comprises prediction circuitry for generating a shift indication based on a prediction of the number of leading zeros that would be present in an output produced by subjecting the operands A and B to an unlike signed addition. Further, result pre-normalization circuitry performs a shift operation on the significands of both operand A and operand B prior to addition of the significands, this serving to discard a number of most significant bits of the significands of both operands as determined by the shift indication in order to produce modified significands for operands A and B. Operand analysis circuitry detects, with reference to the exponents of operands A and B, the presence of a leading bit cancellation condition, and addition circuitry is configured, in the presence of the leading bit cancellation condition, to perform an addition of the modified significands for operands A and B, in order to produce the significand of the result R. Such an approach provides a particularly simple and efficient apparatus for performing addition operations.