Multi-bit Accumulator Using Wallace Trees for CNN MAC Efficiency
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Solution Overview
Problem
Convolutional neural networks (CNNs) face inefficiencies in performing multiplication and accumulation (MAC) operations due to the complexity of dot product computations and accumulation of large numbers of matrices, particularly when executed by general-purpose processors.
Innovation Solution
A multi-bit accumulator apparatus comprising 1-bit Wallace trees, tristate buffers, and a shift-adder, which perform add operations on single-bit input data and accumulate results through shift operations based on clock signals, along with logic gates for signed operations, to enhance the efficiency of MAC operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If general-purpose processors are used to perform MAC operations in CNNs, then versatility is maintained, but computation speed and efficiency deteriorate due to the complexity of dot product computations and accumulation of large numbers of matrices
Solution Approach 1:
The patent segments the MAC operation into distinct functional components: Wallace trees for parallel addition, tristate buffers for controlled output, and shift-adders for accumulation. This segmentation allows each component to be optimized independently, improving overall computation speed while managing complexity through modular design
Solution Approach 2:
The patent introduces tristate buffers as intermediary components between the Wallace trees and shift-adders. These buffers act as mediators that control signal flow and prevent unnecessary toggling, thereby improving efficiency without adding significant complexity to the system
2Area of stationary object
If traditional adder configurations are used in IMC macros, then area efficiency deteriorates due to the large number of full adders required, but computation accuracy is maintained
Solution Approach 1:
The patent merges multiple addition operations into the Wallace tree structure, which performs parallel addition of multiple operands simultaneously. This merging reduces the total number of full adders required compared to traditional sequential addition, thereby improving area efficiency while maintaining or enhancing MAC operation efficiency
Solution Approach 2:
The patent transitions from traditional sequential addition to parallel addition by organizing full adders in a tree structure across multiple dimensions. This dimensional reorganization allows simultaneous computation of multiple partial sums, reducing the number of adders needed and improving area efficiency
3Use of energy by moving object
If enable signals are not properly managed in IMC macros, then power consumption increases due to unnecessary output toggling, but circuit simplicity is maintained
Solution Approach 1:
The patent implements feedback control through enable signals that monitor the state of IMC macros and tristate buffers. This feedback mechanism allows the system to dynamically control output toggling, preventing unnecessary transitions and reducing power consumption while maintaining manageable circuit complexity through systematic signal management
Data Source
AI summary
A multi-bit accumulator including a plurality of 1-bit Wallace trees configured to perform an add operation on single-bit input data, a plurality of tristate buffers configured to output a result of the add operation of the 1-bit Wallace trees, according to an enable signal, and a shift-adder configured to perform an accumulation operation on the result of the add operation of the plurality of 1-bit Wallace trees by a shift operation based on a clock signal.