Vector-by-Matrix Output Block for Analog In-Memory Computing
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Solution Overview
Problem
Existing artificial neural networks face challenges in achieving high-performance information processing due to a lack of adequate hardware technology, particularly in terms of high computational parallelism and energy efficiency, with CMOS-implemented synapses being too bulky for the required number of neurons and synapses.
Innovation Solution
Utilizing non-volatile memory arrays as synapses in neural networks, configured for individual programming, analog programming, and continuous memory state changes, enabling efficient vector-by-matrix multiplication arrays that perform computations in-memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital supercomputers or graphics processing unit clusters are used to achieve high computational parallelism, then computational capability is improved, but energy efficiency deteriorates and cost increases
Solution Approach 1:
The patent replaces traditional digital computing systems (supercomputers, GPUs) with an analog neural network system implemented in non-volatile memory arrays. This substitution enables in-memory computing where synaptic weights are stored directly in memory cells, allowing parallel multiplication operations to occur naturally through Ohm's law and Kirchhoff's current law, thereby achieving high computational parallelism with significantly improved energy efficiency
Solution Approach 2:
The patent changes the fundamental operating parameters from digital binary states to analog continuous values. Non-volatile memory cells operate in analog mode where the resistance or conductance of each cell represents a synaptic weight value, enabling continuous weight adjustment and analog computation. This parameter change allows the system to perform vector-matrix multiplication operations in parallel while consuming minimal energy
2Use of energy by moving object
If CMOS analog circuits are used to implement synapses, then energy efficiency is improved, but device area increases due to bulky circuit implementation
Solution Approach 1:
The patent merges the functions of memory storage and computation into a single integrated structure. Non-volatile memory cells simultaneously serve as both weight storage elements and computational units. The memory array itself performs the multiplication operation through its inherent electrical characteristics, eliminating the need for separate CMOS analog circuitry and thereby reducing device area while maintaining energy efficiency
Solution Approach 2:
The patent extracts the computational function from traditional bulky CMOS analog circuits and relocates it directly into the non-volatile memory array structure. By utilizing the natural electrical properties of memory cells (Ohm's law, Kirchhoff's laws), the system performs computation without requiring additional transistors, capacitors, or other CMOS circuit elements, thus dramatically reducing the area required per synapse
3Area of stationary object
If non-volatile memory arrays are used as synapses, then device area is reduced and computational parallelism is enhanced, but additional output processing circuitry is required
Solution Approach 1:
The patent designs the non-volatile memory array to serve multiple functions simultaneously: weight storage, parallel multiplication computation, and output signal generation. The same memory cells that store synaptic weights also perform the computational operation and generate the resulting current signals. This multi-functionality reduces the need for separate dedicated output processing circuitry while maintaining enhanced computational parallelism and reduced device area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the need for separate multiplication and addition logic circuits, enhances computational parallelism, and improves energy efficiency by performing in-situ memory computation.
Implementation Method 1
Each of the plurality of memory cells store a weight value corresponding to a number of electrons on the floating gate
Implementation Method 2
The plurality of memory cells multiplies the first plurality of inputs by the stored weight values to generate the first plurality of outputs
Data Source
AI summary
In one example, a system comprises: a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an output block coupled to the vector-by-matrix multiplication array comprising: a current-to-voltage converter to convert current received from a column of the vector-by-matrix multiplication array into a voltage, an analog-to-digital converter to convert the voltage into digital bits, and a configuration circuit to convert the digital bits into unsigned digital bits.