Carryless Multiplication via Booth Encoding and XOR Logic
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Solution Overview
Problem
Current microprocessor designs lack a unit capable of performing carryless multiplication efficiently, as existing hardware is unsuitable due to the generation and propagation of carry bits, necessitating separate hardware that increases power consumption and complicates debugging and testing.
Innovation Solution
A method that utilizes existing Booth encoding and compression hardware by preformatting operands into even and odd portions, disabling carry bit propagation, and employing exclusive-OR logic to perform carryless multiplication, allowing for minimal modifications to existing multiplication units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate hardware is added to perform carryless multiplication, then functionality is improved, but device complexity and power consumption increase
Solution Approach 1:
The existing multiplication unit is modified to perform both ordinary and carryless multiplication operations. The same Booth encoder and compressor hardware are used for both operation types, with control signals enabling the unit to switch between functions. This eliminates the need for separate dedicated hardware for carryless multiplication, reducing device complexity while maintaining enhanced functionality.
Solution Approach 2:
The invention changes the operational parameters of the existing multiplication unit by disabling carry propagation during carryless multiplication operations. Control logic modifies the behavior of the compressor to prevent carry bit generation, and the Booth encoder is configured to generate partial products suitable for carryless operation. This parameter change allows the same hardware to perform different mathematical operations.
2Adaptability or versatility
If separate hardware is added to perform carryless multiplication, then functionality is improved, but power consumption increases
Solution Approach 1:
By making the multiplication unit universal, it can perform both ordinary and carryless multiplication using the same physical hardware resources. This avoids the power consumption penalty of maintaining separate dedicated circuits for carryless multiplication, as the same transistors and logic gates are reused for both operation types based on control signals.
3Device complexity
If existing multiplication hardware is used for carryless multiplication, then device complexity is reduced, but reliability may worsen due to modified operations
Solution Approach 1:
The carryless multiplication operation is segmented into distinct phases: Booth encoding of operands, generation of partial products, compression using the existing compressor, and final XOR combination of results. This segmentation allows each stage to be carefully controlled and verified, maintaining reliability while using modified existing hardware.
Solution Approach 2:
Control logic acts as an intermediary between the existing multiplication hardware and the carryless multiplication operation. This control logic manages the modified operation modes, ensures proper signal routing, and coordinates the disabling of carry propagation, thereby maintaining system reliability through structured control of the modified hardware behavior.
Data Source
AI summary
An apparatus having operand registers, an opcode detector, a carryless preformat unit, a compressor, a left shifter, and exclusive-OR logic. The operand registers receive operands for a carryless multiplication. The opcode detector receives a carryless multiplication instruction, and asserts a carryless signal. The carryless preformat unit partitions a first operand into a plurality of parts that are such that a Booth encoder is precluded from selection of second partial products of a second operand, where the second partial products reflect implicit carry operations. The compressor sums first partial products of the second operand via carry save adders arranged in a Wallace tree configuration, where generation of carry bits is disabled. The left shifter shifts one or more outputs of the compressor. The exclusive-OR logic executes an exclusive-OR function to yield a carryless multiplication result.