Computation Using Non-Contact Making Devices TRIZ Cases

Decomposes Softmax into UnNormalized and Normalization operations using reduced precision arithmetic to lower computational overhead in transformer inference.

Cascaded DSP blocks with carry-save adders form large multipliers, eliminating slow carry-propagate delays and preserving general-purpose logic resources.

Segments double-precision matrix multiplication into reduced-precision stages using dynamic scaling factors to recover numerical accuracy on AI accelerators.

A matrix operation apparatus uses nodes with accumulators to perform cumulative addition of element components from column and row inputs.

A matrix multiply-add unit executes a single instruction to perform two-dimensional matrix operations.

In-memory arithmetic processors perform one-step binary operations using two-dimensional memory arrays.

Digit decomposition enables variable-precision computation across 2-bit to 64-bit ranges while reducing latency and wiring congestion in embedded systems.

A multiplier circuit reuses carry-save adder stages to process sub-products early.

A shift-round-and-accumulate circuit executes data shifting, addition, and rounding in one processing cycle using shared adding hardware.

A neural network operation device maps input feature maps and weights to adder tree units for mixed precision processing.

An in-memory computing circuit uses a sense amplifier to compare voltages from memory cells directly within the storage structure.

A daemon caches user proxy settings in a database keyed by session identifiers to eliminate repeated retrieval during package updates.

A hardware crossbar array uses programmable complex-valued electrical admittances to perform multiply-accumulate operations on analog signals.

A reciprocal unit uses lookup tables and a multiplier to compute estimated reciprocals with reduced hardware overhead.

Circuitry detects idempotency in arithmetic operations by comparing result values with input operands to resolve finite precision accuracy issues.

Aligns local metal tracks with global tracks to eliminate dead spaces between in-boundary power-ground cells.

An arithmetic circuit extends the product exponent range to eliminate intermediate normalization shifts, reducing processing cycles for subnormal operands.

A hybrid quantization method applies power-of-two and dynamic fixed-point techniques to deep learning models.

A calculation unit determines square roots of four squares using even number thresholds to accelerate processing.

Adjusting memory cell weights using measured process variation data eliminates error accumulation during neural network operations.

A non-modular multiplier randomizes power consumption patterns during arithmetic operations to obscure side-channel attack vectors.

A computational system inverts multiple floating point denominators using a binary tree structure to compute simultaneous inversions.

Pre-computing inverse matrix elements offline enables deterministic real-time solutions for tokamak plasma control systems.

An integrated circuit FFT engine routes sample streams to a conjugate symmetric combiner for efficient real-valued processing.

Input conversion module inverts the most significant bit of signed multibit data to unsigned format for multiply-accumulate operations.

A processor architecture segments vector processing units into independent columns to execute hardware-supported multiply-accumulate operations.

Segmenting floating-point data into dedicated exponent and mantissa paths eliminates quantization errors while reducing time, area, and power consumption.

Algebraic homomorphisms map non-relevant program statements to identity for compact software verification.

Mapping cooperative thread arrays to result matrix tiles reduces global memory access latency and overcomes bandwidth limitations.

A machine learning algorithm verifies corrected integrated circuit design layouts by identifying features and comparing them against a database.

Segmenting radix-16 computations into radix-4 iterations reduces latency while minimizing storage requirements for partial remainder-divisor tables.

A multiply-accumulate system standardizes input signals to expand output timing.

Processing-in-memory accumulator feeds back latch data to reduce communication latency between separate memory and processor units.

The algorithm reduces clock cycles for cryptographic computations by replacing complex borrow propagation with simplified arithmetic in a redundant basis.

A complex divider generates a third complex value and real number using only adders and bit shifters to replace multiplier circuits.

A redundant numeric representation divides values into overlapping N-bit portions to enable independent parallel processing of floating-point operands.

Lookup tables decompress kernel vectors in a neural processor, reducing CPU reliance and power consumption during machine learning operations.

A physical design-optimal Dadda multiplier architecture delays carry and sum bit processing across multiple stages using ALAP scheduling.

A carryless preformat unit partitions operands for a compressor that sums partial products using exclusive-OR logic.

A tensor processing unit reduces training time by segmenting workloads across homogeneous arrays to resolve the accuracy versus speed trade-off.

Pre-scaling the divisor reduces subtraction iterations, lowering hardware complexity while maintaining calculation accuracy.

An inverse element arithmetic apparatus iterates loops based on bit difference thresholds to minimize approximation errors during finite field calculations.

A calculation apparatus generates prime number information by reversing bits of pre-stored base primes to perform modular multiplication.

Tiling activation data enables adaptive scheduling of multiply-accumulate arrays, reducing power consumption during large tensor processing.

A multiplication accumulation operator shifts mantissa data to align exponents before adding results in an adder tree.

An iterative stage prescales a dividend operand using a reciprocal estimate and redundant number representation to optimize circuit processing.

A carry-ripple adder design reduces logic gates in the carry path using presorted inputs and coding devices.

Mapping cooperative thread arrays to matrix tiles reduces global memory access latency by leveraging local memory bandwidth for concurrent tile computations.

Unrounded result bypass logic forwards intermediate calculation data directly to subsequent fused multiply-addition modules without rounding delays.