Constrained IBPG Cell Placement for IC Layout
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Solution Overview
Problem
Unconstrained placement methods for in-boundary power-ground (IBPG) cells in integrated circuit (IC) layout designs lead to dead spaces between cells, hindering the optimization of standard cell placement and fragmenting the layout, which impedes electronic design automation (EDA) tools in efficiently placing cells.
Innovation Solution
Constrained cell placement is achieved by utilizing IBPG cells with unified power-ground (PG) locations and orientations, ensuring that the first local metal track aligns with one type of global metal track and the second local metal track aligns with another type, thereby eliminating dead spaces between cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If unconstrained placement methods are used for IBPG cells, then placement flexibility is improved, but dead spaces between cells increase and layout fragmentation occurs
Solution Approach 1:
The patent changes the orientation parameter of IBPG cells from unconstrained to constrained (specifically 0 or 90 degrees relative to global metal tracks). This parameter change eliminates dead spaces between cells while maintaining placement flexibility through controlled orientation choices, directly resolving the contradiction between flexibility and dead space reduction.
Solution Approach 2:
The patent introduces asymmetric orientation constraints where IBPG cells must be placed at specific angles (0 or 90 degrees) relative to global metal tracks, rather than allowing symmetric free placement. This asymmetric constraint eliminates irregular dead spaces and improves layout regularity while preserving essential placement flexibility.
2Adaptability or versatility
If unconstrained placement methods are used for IBPG cells, then placement freedom is improved, but layout fragmentation increases
Solution Approach 1:
By changing the orientation parameter to specific discrete values (0 or 90 degrees), the patent ensures that IBPG cell boundaries align with global metal tracks, creating continuous and regular layout structures. This maintains placement freedom through controlled choices while eliminating layout fragmentation.
Solution Approach 2:
The patent enforces homogeneous orientation across all IBPG cells, requiring them to align with global metal track directions. This homogeneity eliminates irregular gaps and fragmentation, creating a consistent and continuous layout structure while preserving placement flexibility through the two allowed orientations.
3Area of stationary object
If constrained cell placement with unified PG locations is used, then dead spaces are reduced, but placement constraints increase
Solution Approach 1:
The patent simplifies placement constraints by defining only two specific orientation parameters (0 or 90 degrees) relative to global metal tracks. This minimal parameter constraint effectively reduces dead spaces while maintaining low complexity, as EDA tools can easily handle these discrete orientation choices without complex optimization.
Data Source
AI summary
The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.