Physical Design-Optimal Dadda Multiplier Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Wide integer multipliers face bottlenecks in area requirements and performance due to clock cycle limitations, especially as operand size increases, leading to combinatorial delay issues and the need for pipelined approaches with multiple latches.
Innovation Solution
Implementing a physical design-optimal Dadda architecture that delays the processing of carry and sum bits by as many stages as possible, using ALAP scheduling, which spreads combinatorial logic evenly across stages, allowing for pipeline multiplication at any stage and reducing the number of latch stages required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional Wallace-tree or Dadda-tree methods are used to accumulate partial products, then the required gate count and critical path delay are reduced, but area requirements and performance bottlenecks worsen as operand size increases
Solution Approach 1:
The patent segments the partial product accumulation into multiple stages, where each stage processes a subset of columns. This segmentation allows the design to handle large operand sizes by dividing the computation into manageable chunks, reducing the area requirements for each individual stage while maintaining overall multiplication performance.
Solution Approach 2:
The patent introduces a new dimension to the traditional Dadda-tree by implementing carry and sum bit processing in a separate third dimension (time/stage). Instead of processing all bits simultaneously in a single plane, the invention spreads the processing across multiple stages, with each stage handling specific bit positions, thereby reducing area requirements while maintaining productivity.
2Area of stationary object
If pipelined approaches with multiple latches are used to handle large operands, then area requirements are reduced, but combinatorial delay spikes occur in the first stage
Solution Approach 1:
The patent applies preliminary action by pre-processing carry and sum bits in earlier stages before they reach the critical first stage of the pipeline. By anticipating and handling these bits in advance across multiple stages, the design eliminates combinatorial delay spikes that would otherwise occur when all bits converge simultaneously in the first stage.
Solution Approach 2:
The patent implements dynamics by making the processing depth of each stage variable rather than fixed. Each stage dynamically adjusts its processing depth based on the specific bit positions it handles, allowing for optimized timing and reducing combinatorial delay while maintaining area efficiency. This dynamic approach enables flexible pipeline staging adapted to the specific multiplication operation.
Data Source
AI summary
Aspects of the invention include physical design-optimal Dadda architectures that scale with increasing operand size. Partial product arrays can be generated for two n-bit operands and columns in the partial product arrays can be shifted to a first row. The number of partial products in each column can be iteratively reduced across one or more stages until each column has at most two partial products. At each stage a maximum column height is determined and each column having a height greater than the maximum column height is reduced using half-adders and full-adders. Result bits of the half-adders and the full-adders are placed at the bottom of the current column and carry bits of the half-adders and the full-adders are placed at the bottom of the next column.