In-Memory Arithmetic Processors for One-Step Binary Operations
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Solution Overview
Problem
The Von Neumann computing architecture is inefficient due to the need for multiple steps of binary code manipulation for arithmetic operations, leading to increased power consumption and data traffic, particularly at the single-bit level, resulting in computation bottlenecks and memory congestion.
Innovation Solution
Implementing in-memory arithmetic processors with built-in arithmetical tables that allow for one-step processing of binary numbers by using two-dimensional memory arrays to store and retrieve resultant binary codes directly, eliminating the need for tedious bit-level manipulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Von Neumann architecture with sequential binary code manipulation is used, then computation can be performed with standard logic gates and registers, but power consumption increases and data traffic increases due to multiple manipulation steps
Solution Approach 1:
The patent merges the computation and memory functions into a single integrated structure. The arithmetic processing is performed directly within the memory array by utilizing the stored binary code patterns themselves as the computational resource, eliminating the need for separate logic gates and registers that would consume additional power for data manipulation.
Solution Approach 2:
The patent extracts the arithmetic computation function from the traditional CPU logic units and relocates it directly into the memory array. By storing pre-computed arithmetic result patterns in the memory cells, the system eliminates the need for power-consuming sequential logic operations and carries, achieving computation through direct memory pattern retrieval.
2Measurement precision
If multiple steps of binary code manipulation are used for arithmetic operations, then accurate computation can be achieved, but data traffic increases causing Von Neumann bottleneck and computation efficiency decreases
Solution Approach 1:
The patent performs preliminary computation by pre-storing the results of arithmetic operations (such as addition, subtraction, multiplication, division) directly in the memory array as binary code patterns. When a computation is needed, the system simply retrieves the pre-computed result pattern from memory based on the input operands, eliminating the need for real-time sequential manipulation steps and achieving both accuracy and efficiency.
3Adaptability or versatility
If sequential instruction-based arithmetic operations are used, then computation can be performed with standard CPU architecture, but memory storage space for instruction codes increases and processing speed decreases
Solution Approach 1:
The patent makes the memory array universal by enabling it to perform multiple arithmetic operations (addition, subtraction, multiplication, division) directly within its structure. The same memory array can compute different arithmetic functions by selecting different pre-stored result patterns, eliminating the need for separate instruction code storage and making the memory system multi-functional for both data storage and computation.
Data Source
AI summary
In-memory arithmetic processors for the “n-bit” by “n-bit” multiplication, the “n-bit” by “n-bit” addition, and the “n-bit” by “n-bit” subtraction operations are disclosed. The in-memory arithmetic processors of the invention can obtain the operational resultant integer in the binary format for two inputted integers represented by two “n-bit” binary codes in one-step processing with no sequential multiple-step operations as for the conventional arithmetic binary processors. The in-memory arithmetic processors are implemented by a 2-dimensional memory array with X and Y decoding for the two inputted operational integers in the arithmetic binary operations.