FFT Engine with Conjugate Symmetric Combiner for Real-Valued Processing
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Solution Overview
Problem
Existing hardware solutions for performing fast Fourier transforms (FFTs) are inefficient in handling real-valued and complex-valued data, particularly in applications like FMCW radar, audio processing, and telecommunications, where real-valued FFTs are needed but not adequately supported.
Innovation Solution
An integrated circuit (IC) with a fast Fourier transform (FFT) engine, memory, conjugate symmetric combiner, and control circuit is designed to selectively perform real-valued FFTs, real inverse FFTs, complex FFTs, and complex inverse FFTs, enabling efficient processing of real-valued data streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing hardware solutions are used for performing FFTs, then complex-valued FFT operations are supported, but real-valued FFT operations are inefficient and not adequately supported
Solution Approach 1:
The hardware accelerator is designed to perform multiple types of FFT operations (real-valued FFT, real-valued IFFT, complex-valued FFT, and complex-valued IFFT) using a unified architecture. The same FFT engine and memory structure handle both real and complex inputs by adjusting the data formatting and processing mode, eliminating the need for separate dedicated hardware for each operation type.
Solution Approach 2:
The FFT computation is divided into two distinct phases: an initial phase where the FFT engine processes input samples and stores results in memory, and a second phase where the conjugate symmetric combiner retrieves and combines stored samples to produce the final real-valued output. This segmentation allows the hardware to optimize each phase independently while maintaining high throughput.
2Productivity
If real-valued FFT is performed using existing hardware, then computational operations are executed, but memory requirements and computational complexity are high
Solution Approach 1:
During the first phase, the FFT engine pre-computes the transform of the input real-valued samples and stores the complex-valued results in memory before the final combination step. This preliminary action allows the second phase to simply retrieve and combine pre-computed values rather than performing redundant calculations, significantly reducing the computational burden during output generation.
Solution Approach 2:
The system stores intermediate complex-valued FFT results in memory and reuses these stored values during the combination phase. Instead of recalculating transforms, the conjugate symmetric combiner copies and combines previously computed results, reducing both memory bandwidth requirements and computational complexity compared to direct real-valued FFT implementation.
Data Source
AI summary
In described examples, an integrated circuit (IC) includes a fast Fourier transform (FFT) engine, a first memory, a second memory, a conjugate symmetric combiner (CSC), and a control circuit coupled to control them. The first and second memories are coupled to the FFT engine, and the CSC is coupled to the first and second memories and the FFT engine. The FFT engine receives and processes a first stream of samples to generate a second stream of samples. In a first phase, the FFT engine provides a first portion of the second stream of samples to the first memory. In a second phase, the FFT engine provides a second portion of the second stream of samples to the second memory, the first memory provides the first portion of the second stream of samples to the CSC, and the CSC responsively generates a third stream of samples.