Chained DSP Blocks for Large Multiplier Implementation
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Solution Overview
Problem
Existing programmable logic devices (PLDs) face inefficiencies when performing large multiplications, as they require users to program logic outside specialized processing blocks, leading to slow and resource-intensive operations, especially for double-precision or larger complex multiplications, due to reliance on carry-propagate adders and general-purpose resources.
Innovation Solution
The solution involves chaining multiple fine-grained DSP blocks with carry-save adders to perform large multiplications, minimizing propagation delay and reducing reliance on general-purpose resources, using carry-save adders for partial sum/carry signal propagation and a carry-propagate adder for the final output, allowing for efficient creation of large multipliers without needing core logic circuits or interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple DSP blocks are chained to perform large multiplications using general-purpose programmable logic, then the multiplication capability is extended to larger sizes, but the operation speed decreases and resource consumption increases due to reliance on carry-propagate adders
Solution Approach 1:
The patent segments the large multiplication operation into multiple smaller multiplication operations performed by individual DSP blocks. Each DSP block handles a portion of the multiplication (e.g., 18-bit by 18-bit), and the partial results are combined through chaining. This segmentation allows the system to achieve large multiplication capability while maintaining speed by using fast carry-save adders within each segment rather than slow carry-propagate adders for the entire operation.
2Adaptability or versatility
If general-purpose programmable logic is used to interconnect multipliers for large multiplications, then larger multiplication sizes are achieved, but resource availability decreases as general-purpose resources are consumed
Solution Approach 1:
The patent merges multiple DSP blocks into a chained configuration where the output of one DSP block feeds into the next, creating a unified large multiplication unit. The combining circuitry within each DSP block integrates partial sum/carry signals from multiple multipliers and from adjacent DSP blocks, eliminating the need for external general-purpose logic interconnections. This merging approach achieves large multiplication capability while preserving general-purpose resource availability.
3Ease of manufacture
If carry-propagate adders are used for addition operations in multipliers, then the implementation is simpler, but the propagation delay increases making the operation slower
Solution Approach 1:
The patent changes the operational parameters of the adder by using carry-save adders instead of carry-propagate adders within the DSP blocks. Carry-save adders operate by saving carries for later processing rather than immediately propagating them, which significantly reduces propagation delay. The carry propagation is deferred to the final combining stage, allowing parallel processing within each DSP block and achieving faster overall multiplication performance.
Data Source
AI summary
A programmable integrated circuit device includes a plurality of specialized processing blocks. Each specialized processing block may be small enough to occupy a single row of logic blocks. The specialized processing blocks may be located adjacent one another in different logic block rows, forming a column of adjacent specialized processing blocks. Each specialized processing block includes one or more multipliers based on carry-save adders whose outputs are combined using compressors. Chain-in and chain-out connections to the compressors allow adjacent specialized processing blocks to be cascaded to form arbitrarily large multipliers. Each specialized processing block also includes a carry-propagate adder, and the carry-propagate added in the final specialized processing block of the chain provides the final result. The size of the multiplication that may be performed is limited only by the number of specialized processing blocks in the programmable integrated circuit device.