Memory Cell Value Recalibration for ANN Error Reduction

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Solution Overview

Problem

Process variations in memory cells lead to errors in the output of artificial neural networks (ANNs) due to variations in voltage-conductance characteristics, causing progressive error accumulation during MAC operations.

Innovation Solution

The values stored in memory cells, such as weights of an ANN, are updated based on process variation characteristics to recalibrate and reduce error accumulation, by incrementing or decrementing the values to account for the variations in memory cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If values are stored in memory cells for ANN operations, then the computing device can perform neural network operations, but process variations cause voltage-conductance characteristic deviations leading to output errors

Engineering Contradiction:
Improveneural network operation capabilityVSAvoidoutput accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by measuring process variation characteristics of memory cells before storing ANN values, and pre-compensating for these variations by adjusting the values to be stored. This upfront calibration eliminates the need for real-time correction during neural network operations, thereby maintaining both productivity and reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the parameters (values) to be stored in memory cells based on measured process variation characteristics. By adjusting these parameters according to actual memory cell behavior, the system compensates for manufacturing variations and ensures accurate neural network outputs despite hardware imperfections.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If process variation characteristics are measured and values are updated to compensate, then output accuracy is improved, but additional processing steps and time are required

Engineering Contradiction:
Improveoutput accuracyVSAvoidvalue update processing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The compensation process is performed in advance during memory cell initialization or configuration, rather than during actual neural network computations. This timing strategy minimizes the impact on computational productivity while achieving the goal of improving measurement precision and output accuracy.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If values are incremented or decremented to account for process variations, then error propagation is reduced, but the complexity of the storage and retrieval process increases

Engineering Contradiction:
Improveerror propagation controlVSAvoidvalue modification process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent modifies the values to be stored in memory cells based on measured process variation characteristics. This parameter adjustment approach systematically compensates for manufacturing variations without requiring complex real-time correction circuits, thereby improving reliability while maintaining relatively simple device architecture.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250045019A1Value update using process variation
Publication Date: 2025.02.06 MICRON TECHNOLOGY INC
  • US20250045019A1 patent drawing
  • US20250045019A1 patent drawing
  • US20250045019A1 patent drawing

AI summary

Modifying values stored in memory cells based on process variation can include receiving process variation information for a first plurality of memory cells of a memory array. A plurality of values to be stored in the memory cells can be modified based on the process variation information. The plurality of instructions to store the plurality of values in a second plurality of memory cells can be compiled. The plurality of modified values can also be stored in a second plurality of memory cells at run time.