Multi-Precision Division Algorithm Using Redundant Number Representation
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Solution Overview
Problem
Current multi-precision division methods in cryptosystems are computationally expensive and consume a large number of clock cycles, leading to reduced speed and increased power consumption, particularly in devices with limited power such as smart cards.
Innovation Solution
An optimized multi-precision division process is implemented by iteratively performing subtraction and addition operations on multi-precision numbers, reducing the number of clock cycles required and optimizing modular reduction operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multi-precision division is performed by CPU or ALU using conventional methods, then the division operation can be completed, but it consumes a large number of clock cycles leading to reduced speed and increased power consumption
Solution Approach 1:
The patent changes the operational parameters of the division algorithm by using a redundant number system representation and modified iteration steps. The division process is restructured to perform operations in a redundant basis where addition and subtraction are simplified, reducing the computational complexity per iteration and overall clock cycle requirements.
Solution Approach 2:
The patent replaces the conventional mechanical division algorithm (which relies on repeated subtraction with complex borrow propagation) with an optimized algorithm that uses redundant number representation. This substitution eliminates the need for complex borrow/carry propagation mechanisms, significantly reducing the number of clock cycles required.
2Reliability
If multi-precision division is performed by CPU or ALU using conventional methods, then the division operation can be completed, but power consumption increases
Solution Approach 1:
The patent changes the computational parameters by operating in a redundant number system where arithmetic operations require fewer clock cycles. Since power consumption in digital circuits is directly related to the number of clock cycles and switching operations, this parameter change reduces power consumption while maintaining division accuracy.
Solution Approach 2:
The optimized algorithm maintains continuous useful action by reducing idle clock cycles and unnecessary operations. The redundant number system allows for more direct computation paths, eliminating wasted computational steps that would otherwise consume power without contributing to the division result.
3Productivity
If conventional multi-precision division algorithms are used in cryptosystems, then modular reduction can be performed, but the computational cost is high
Solution Approach 1:
The patent changes the algorithmic parameters by using redundant number representation and modified iteration steps. This transforms the complex conventional division algorithm into a simpler form that requires fewer computational operations, thereby increasing cryptographic computation throughput while reducing algorithmic complexity.
Solution Approach 2:
The patent segments the division process into distinct phases: initialization with redundant number conversion, iterative division in the redundant basis, and final conversion back to standard representation. This segmentation allows each phase to be optimized independently, reducing overall algorithmic complexity while improving productivity.
Data Source
AI summary
In an embodiment, multi-precision numbers A and B are accessed from a storage device (e.g., a memory array), where A is a dividend and B is a divisor. A multi-precision division operation is iteratively performed on the numbers A and B including: performing a multi-precision subtraction operation on A and B during a first iteration of the multi-precision division operation; performing a multi-precision addition operation on A and B during a second iteration of the multi-precision division operation as a result of a determination that a final borrow occurred during the subtraction operation; and performing a multi-precision addition operation on A and B after a final iteration of the multi-precision division operation.