Redundant Numeric Representation for Parallel Floating-Point Processing
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Solution Overview
Problem
Floating-point arithmetic is non-associative, leading to reproducibility issues and inefficiencies in parallel processing due to rounding and normalization, making it difficult to achieve consistent results when adding or subtracting numbers in a different order.
Innovation Solution
The use of a redundant representation, such as the Redundant High-Precision Anchor (RHPA) format, which allows for parallel processing by dividing data into N-bit portions with overlapping significance, enabling independent operations on each portion without carrying between lanes, thus maintaining associativity and reproducibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating-point arithmetic is performed sequentially to ensure reproducible results, then reliability is improved, but productivity deteriorates
Solution Approach 1:
The patent divides the floating-point number into multiple N-bit portions (e.g., four 16-bit portions for a 64-bit float), where each portion can be processed independently in parallel. This segmentation allows simultaneous computation of multiple portions while maintaining reproducible results through the redundant representation scheme.
Solution Approach 2:
The patent changes the representation parameter from standard floating-point format to a redundant representation format with overlapping bits. This parameter change enables parallel processing of N-bit portions while preserving the ability to generate reproducible results, resolving the contradiction between reliability and productivity.
2Productivity
If floating-point arithmetic is parallelized to improve processing speed, then productivity is improved, but reliability deteriorates due to non-associative operations
Solution Approach 1:
By segmenting the floating-point number into independent N-bit portions with redundant representation, the patent enables parallel processing of each segment without affecting the overall reproducibility. Each segment can be computed simultaneously while the redundant structure ensures consistent results.
Solution Approach 2:
The redundant representation acts as an intermediary structure that mediates between parallel processing requirements and reproducibility requirements. The overlapping bits in the redundant representation serve as a buffer that allows parallel operations to proceed while maintaining the ability to generate reproducible results.
3Device complexity
If standard floating-point representation is used, then device complexity is reduced, but productivity deteriorates due to sequential processing requirements
Solution Approach 1:
The patent segments the floating-point representation into multiple N-bit portions that can be processed in parallel. This segmentation increases parallel processing capability while the segmented structure itself manages the complexity through modular organization of the redundant representation.
Solution Approach 2:
By changing the representation parameter to include redundant overlapping bits, the patent enables parallel processing capability. The parameter change from standard to redundant representation is the key enabler for productivity improvement while keeping the overall structure manageable.
Data Source
AI summary
A redundant representation is provided where an M-bit value represents a P-bit numeric value using a plurality of N-bit portions, where M>P>N. An anchor value identifies the significance of bits of each N-bit, and within a group of at least two adjacent N-bit portions, two or more overlap bits of a lower N-bit portion of the group have a same significance as two or more least significant bits of at least one upper N-bit portion of the group. A plurality of operation circuit units can perform a plurality of independent N-bit operation in parallel, each N-bit operation comprising computing a function of corresponding N-bit portions of at least two M-bit operand values having the redundant representation to generate a corresponding N-bit portion of an M-bit result value having the redundant representation. This enables fast associative processing of relatively long M-bit values in the time taken for performing an N-bit operation.