Multiplication Accumulation Operator for Neural Network Processing

The patent merges the processor and memory into a single integrated PIM device, where computation units are directly coupled to memory cells. This integration eliminates the need for separate data communication channels between processor and memory, allowing data to be processed in-place without transmission delays, thereby resolving the contradiction between structural simplicity and processing speed.

The patent introduces sense amplifiers as intermediary components that directly couple memory cells to computation units. These sense amplifiers serve as mediators that enable direct reading and processing of data from memory cells without requiring traditional data bus communication, thus improving data processing speed while maintaining manufacturing feasibility through standardized memory cell designs.

The PIM device enables self-service computation by performing arithmetic operations directly within the memory array. Each memory cell can be read and processed by its associated computation unit without requiring data to be transferred to external processors. This self-contained computation capability allows deep neural networks to be executed with high throughput, resolving the contradiction between accuracy (requiring many layers) and productivity (computation speed).

The patent segments the neural network computation into distributed operations across multiple PIM cores, each handling specific matrix multiplication and accumulation tasks. This segmentation allows parallel execution of multiple neural network layers simultaneously, increasing overall computation throughput while maintaining the accuracy benefits of deep architectures.