PIM Accumulator with Latch Feedback for MAC Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Deep learning neural networks require increased computational resources due to the need for larger neural networks, leading to performance degradation in AI systems with separate memory and processor units, as data communication limitations hinder efficient processing.
Innovation Solution
A PIM device integrates processor and memory on a semiconductor chip, enabling direct arithmetic operations and improving data processing speed by incorporating a MAC operator with an accumulator and latch circuit for accumulative addition, and a command decoder for controlling MAC operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If separate memory and processor units are used, then device complexity is reduced, but data communication latency increases and processing speed deteriorates
Solution Approach 1:
The patent combines memory and processor units into a single integrated PIM device, where memory cells directly perform MAC operations with weight data stored in the same memory array. This eliminates data communication latency between separate memory and processor units while maintaining manageable device complexity through the unified architecture.
2Productivity
If larger neural networks are deployed, then AI performance improves, but computational resource requirements increase
Solution Approach 1:
The patent divides the computational task into fine-grained MAC operations performed at the memory cell level. Each memory cell independently performs multiply-accumulate operations on weight data and input data, segmenting the overall computation across numerous parallel units. This enables larger neural networks to be processed by distributing computational work across the memory array rather than requiring a single complex processor.
Solution Approach 2:
The patent transitions computation from a traditional processor dimension to the memory array dimension by performing MAC operations directly within the memory cells. This dimensional shift allows computational capacity to scale with memory capacity, enabling larger neural networks to be supported by simply increasing memory array size rather than requiring proportionally more complex processing units.
3Measurement precision
If accumulative addition operations are performed with feedback, then MAC operation accuracy improves, but circuit complexity increases
Solution Approach 1:
The patent implements feedback mechanisms where the output of MAC operations is fed back to the accumulation adder for subsequent accumulative addition operations. The latch circuit stores intermediate results and feeds them back to maintain running sums, improving MAC operation accuracy through multi-stage accumulation while managing circuit complexity by reusing existing circuit elements across multiple operation cycles.
Data Source
AI summary
An accumulator according to an embodiment of the present disclosure includes an accumulation adder configured to perform an accumulative addition operation on input data and latch data that are input through a first input terminal and a second input terminal, respectively, to generate accumulation data, and a latch circuit, including a plurality of flip-flops, each of the plurality of flip-flops configured to receive the accumulation data and capable of latching and outputting the accumulation data as the latch data, wherein one of the latch data that is output from each of the plurality of flip-flops is selected to be fed back to the accumulation adder based on a first accumulation control signal. The latch circuit is configured to latch the accumulation data in the flip-flop, among the plurality of flip-flops, selected by a second accumulation control signal.