Cascade Chip ID Generation Circuits for Stacked Memory Initialization

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Solution Overview

Problem

Existing semiconductor memory devices require external initialization to determine chip identification numbers, which can be cumbersome and inefficient, especially in stacked memory chip configurations where each chip needs to be individually identified.

Innovation Solution

Incorporating chip identification (ID) generation circuits in each memory chip, connected in a cascade configuration, which are activated by a power supply voltage to automatically generate unique ID numbers, eliminating the need for external commands and simplifying the initialization process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If external initialization is used to determine chip identification numbers, then the identification process can be performed, but the process becomes cumbersome and inefficient

Engineering Contradiction:

Improveinitialization efficiencyVSAvoidinitialization complexity

Core Design Contradiction:

ProductivityVSEase of operation

Solution Approach 1:

The chip ID generation circuit enables each memory chip to automatically generate its own identification number without requiring external initialization commands. The circuit activates upon power supply application and autonomously produces the chip ID, eliminating the need for external processor intervention and significantly improving initialization efficiency

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The chip ID generation circuit is designed to activate automatically upon power supply application, performing the identification function before normal operations begin. This preliminary action ensures that chip IDs are ready before the host processor needs to access the memory chips, streamlining the initialization sequence

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If multiple memory chips are stacked together, then device integration is improved, but the number of vias required increases complexity

Engineering Contradiction:

Improvestacking capabilityVSAvoidvia structure complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The chip ID generation circuit uses segmented signaling where each chip in the stack generates and transmits its ID through dedicated TSVs. This segmentation allows each chip to be independently identified without requiring complex cross-chip communication structures, reducing overall device complexity while maintaining stacking capability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The chip ID generation circuit acts as an intermediary that simplifies the interaction between stacked memory chips and the external host processor. By generating and outputting chip IDs automatically, the circuit mediates the identification process without requiring complex external control logic or additional via structures

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9129663B2Semiconductor memory device including plurality of memory chips

Publication Date: 2015.09.08 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips