Cascade Via Stacking for Shorter Signal Paths in Optical Semiconductors
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Solution Overview
Problem
The scaling down of optical semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly in signal transfer and energy consumption.
Innovation Solution
The design incorporates a logic die, a memory die, and a sensor die with specific via structures, including a first inter-die via and intra-die vias, which electrically couple the sensor die to the logic die, simplifying the sensor die's fabrication and reducing signal path length, thereby improving yield and energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimensions of optical semiconductor devices are scaled down, then computing ability is improved, but quality, yield, performance, and reliability deteriorate while complexity increases
Solution Approach 1:
The device is divided into multiple functional dies (sensor die, logic die, memory die) that are stacked together. Each die is fabricated separately using optimized processes for its specific function, then integrated through inter-die vias. This segmentation allows each die to be scaled and optimized independently, improving overall device performance while managing complexity through modular design.
Solution Approach 2:
The patent transitions from a planar 2D architecture to a three-dimensional stacked architecture. Multiple dies are arranged vertically along the z-axis, creating inter-die via connections that traverse through the stack. This dimensional change increases computing density and ability while managing signal transfer complexity through vertical integration rather than lateral routing.
2Productivity
If the dimensions of optical semiconductor devices are scaled down, then computing ability is improved, but yield deteriorates
Solution Approach 1:
By segmenting the device into separate functional dies, each die can be fabricated and tested independently before final assembly. This allows for better yield management as defects can be identified and addressed at the die level rather than affecting the entire device, improving overall manufacturing yield while maintaining scaled-down dimensions.
3Productivity
If the dimensions of optical semiconductor devices are scaled down, then computing ability is improved, but performance deteriorates
Solution Approach 1:
The vertical stacking architecture with direct inter-die via connections creates shorter signal paths compared to lateral routing in planar designs. Signals travel vertically through the stack rather than across the surface, reducing transmission distance and improving signal transfer speed despite the scaled-down dimensions of individual components.
4Productivity
If the dimensions of optical semiconductor devices are scaled down, then computing ability is improved, but reliability deteriorates
Solution Approach 1:
Segmenting the device into separate functional dies allows each die to be optimized and tested independently for reliability. The modular architecture enables better stress distribution and fault isolation, where a failure in one die does not necessarily propagate to other dies, thereby improving overall device reliability despite scaled-down dimensions.
5Ease of manufacture
If cascade vias are used to electrically couple sensor die to logic die, then fabrication complexity is reduced, but via height increases
Solution Approach 1:
The electrical coupling path is segmented into inter-die vias that pass through dedicated interface regions (memory peripheral area) rather than requiring long lateral connections. This segmentation of the signal path into vertical inter-die segments simplifies fabrication by using standard via processes, even though the vertical height of individual vias increases compared to short lateral connections.
Data Source
AI summary
An optical semiconductor device with cascade vias is disclosed. The semiconductor device a logic die having a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and having a memory cell area and a memory peripheral area; a first inter-die via positioned in the memory peripheral area; a landing pad positioned on the first inter-die via; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area. The first inter-die via and the first intra-die via are electrically coupled through the landing pad in a cascade manner.