Cascaded Dual-Loop PLL With AC-Coupled Charge Pump for Low Phase Noise
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Solution Overview
Problem
Conventional charge pump designs for phase-locked loops (PLLs) suffer from performance limitations due to charge sharing and channel length modulation issues, leading to phase noise degradation and jitter, especially in millimeter wave and terahertz ranges.
Innovation Solution
A cascaded PLL architecture is introduced, comprising a type-II loop stage operating at a low frequency and a dual-path loop stage at a higher frequency, utilizing an AC-coupled charge pump (ACCP) to isolate the loop filter and a wideband dual-path loop to attenuate phase noise, along with optimized VCO tuning ranges to maintain low jitter and wide frequency tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If conventional charge pump designs are used with small transconductance to minimize noise, then phase noise is reduced, but the offset current due to charge sharing increases and matches the biasing current level, degrading phase noise performance
Solution Approach 1:
The charge pump is segmented into two independent pumps (first charge pump and second charge pump) operating at different frequencies. The first charge pump operates at a lower frequency to minimize noise, while the second charge pump operates at a higher frequency to provide sufficient charging current. This segmentation allows each pump to be optimized for its specific function without the trade-off present in conventional single-pump designs.
Solution Approach 2:
The invention changes the operating frequency parameter of the charge pump by using two different frequencies (first frequency and second frequency) for the two charge pumps. This parameter change enables the system to achieve both low noise (through the lower frequency pump) and sufficient charging current (through the higher frequency pump), resolving the contradiction between noise minimization and performance reliability.
2Object-generated harmful factors
If the transconductance of the charge pump is kept small to minimize noise, then noise is reduced, but the channel length must be increased for better matching, which increases parasitic capacitance and offset current
Solution Approach 1:
The charge pump function is segmented into two independent charge pumps operating at different frequencies. This allows the transconductance devices in each pump to be optimized independently - the first pump can use smaller channel lengths since it operates at lower frequency with less noise concern, while the second pump provides the necessary charging current.
Solution Approach 2:
The invention uses partial action by having the first charge pump handle the noise-critical portion of the charging function at lower frequency, while the second charge pump provides additional charging capability at higher frequency. This partial division of functionality allows each pump to operate in its optimal regime without requiring excessive channel lengths.
3Device complexity
If a single-stage PLL is used, then the structure is simple, but phase noise degradation and jitter issues occur in millimeter wave and terahertz ranges
Solution Approach 1:
The PLL is segmented into two independent stages: a first PLL operating at a lower frequency and a second PLL operating at a higher frequency (integer multiple of the first). This segmentation allows the first PLL to provide a clean reference signal with low phase noise, while the second PLL generates the high-frequency output signal. The cascaded structure resolves the contradiction by distributing the functionality across two simpler stages rather than one complex single-stage PLL.
Solution Approach 2:
The invention transitions from a single-frequency operation to a two-frequency dimensional approach. The first PLL operates at frequency f1 and the second PLL operates at frequency N×f1, where N is an integer greater than 2. This frequency dimensionality allows the system to achieve low phase noise at the reference frequency while generating high-frequency output, overcoming the limitations of single-stage PLLs in millimeter wave and terahertz ranges.
4Adaptability or versatility
If conventional single-loop PLL architecture is used, then the design is straightforward, but tuning range is limited and phase noise performance degrades at high frequencies
Solution Approach 1:
The PLL system is segmented into two cascaded loops with different frequency ranges. The first PLL covers a lower frequency range and provides a clean reference signal, while the second PLL covers a higher frequency range and provides the final output. This segmentation enables the system to achieve both wide tuning range (by combining the ranges of both PLLs) and low phase noise (by having the first PLL clean up reference noise before it enters the second PLL).
Solution Approach 2:
The invention extends the frequency dimension by using two PLLs operating at different frequency levels. The first PLL operates at a base frequency and the second PLL operates at an integer multiple of that frequency. This frequency dimensionality allows the system to achieve wide overall tuning range while maintaining low phase noise through the reference cleaning effect of the first PLL.
Data Source
AI summary
A cascaded phase-locked loop (PLL) architecture including voltage-controlled oscillators (VCO) may operate in the mmWave and terahertz range. The architecture may include a low-jitter type-II radio-frequency PLL as a first stage and a wideband high-frequency dual-path PLL as a second stage. By using the radiofrequency output from the first stage as a reference, the second stage attenuates VCO phase noise, resulting in reduced overall jitter. Additionally, the first stage may include an AC-coupled charge pump to ensure robust phase noise performance across a wide VCO control voltage range, and a VCO tuning range design scheme may be provided to achieve a wide tuning range without sacrificing jitter performance.