Cascaded RC Glitch Filter for Low-Skew Noise-Immune IC Interfaces
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Solution Overview
Problem
Low frequency interfaces in Integrated Circuits (ICs) prone to picking up external noise due to low slew rates, leading to timing and functional failures, and conventional glitch filters suffer from duty cycle distortion, pulse clipping, and supply noise susceptibility.
Innovation Solution
A glitch filter with at least two coupled RC filters and feedback/feedforward switches to minimize delay skews and stabilize output voltages, preventing noise in output signals by efficiently pulling up or down the output voltage based on input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional analog RC circuit is used as a glitch filter, then glitches of specified pulse widths can be suppressed, but duty cycle distortion and pulse clipping occur
Solution Approach 1:
The glitch filter is divided into multiple independent RC filter stages (first RC filter, second RC filter) with different time constants. Each stage targets specific glitch pulse widths, allowing selective suppression while preserving valid signal pulses. This segmentation enables the filter to handle different glitch durations without causing uniform distortion to all signals.
Solution Approach 2:
Different RC time constants are used in different filter stages to create frequency-selective glitch suppression. The first RC filter uses a longer time constant for suppressing wider glitches, while the second RC filter uses a shorter time constant for narrower glitches. This parameter variation allows precise control over which pulse widths are suppressed without affecting valid signals.
2Reliability
If a conventional analog RC circuit is used as a glitch filter, then glitches can be suppressed, but supply noise susceptibility increases
Solution Approach 1:
Feedback switches are implemented to detect and correct output voltage deviations caused by supply noise. When supply voltage fluctuates, the feedback mechanism activates switches that pull the output voltage back to its correct logic level, compensating for the noise effect and maintaining signal integrity despite analog RC filter stages.
3Use of energy by moving object
If low frequency interfaces are used in ICs, then power consumption is reduced, but external noise pickup increases due to low slew rates
Solution Approach 1:
Multiple RC filter stages with different time constants provide multi-level noise filtering. The first stage filters broader frequency noise, while the second stage targets higher frequency glitches. This segmented approach enables effective noise rejection in low slew rate conditions without requiring high-frequency operation that would increase power consumption.
Solution Approach 2:
The RC filter stages act as intermediary elements between the low frequency interface and the digital logic. These analog filters gradually attenuate noise components before signals reach the digital domain, allowing low frequency operation with reduced power consumption while still achieving noise immunity through the filtering action.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses glitches, reduces delay skews, and enhances noise immunity, resulting in sharper rising and falling edges of output signals, immune to supply noise and pulse width variability.
Implementation Method 1
A glitch filter with at least two coupled RC filters to minimize delay skews based on a RC filter or an inverter of the glitch filter
Implementation Method 2
Another aspect of the present invention provides a glitch filter with feedback and feedforward switches coupled to a RC filter to efficiently pull up or pull down an output voltage of the RC filter to rails and prevent noises in output signals of the glitch filter
Data Source
AI summary
An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switch to the feedback switches to accelerate the pull up or the pull down.


