Cascode Buffer Circuit for Stable Current Across Wide Supply Voltages
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Solution Overview
Problem
Conventional high voltage constant current buffer driver circuits experience increased output current variations with changing supply voltages, leading to potential over-driving of NPN bipolar junction transistors and increased propagation delay in Intelligent Power Modules.
Innovation Solution
A high voltage constant current buffer circuit design incorporating a high voltage current mirror with a low-voltage PMOS transistor and a high-voltage PMOS transistor in a Cascode configuration, along with a transient current boosting circuit to stabilize output current across a wide voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional high voltage constant current buffer driver circuits are used to operate at wide voltage range, then the circuit can adapt to different supply voltages, but the output current varies dramatically with supply voltage changes
Solution Approach 1:
The patent employs a composite transistor structure combining high-voltage and low-voltage transistors to dynamically adjust the output characteristics. The high-voltage transistor handles the wide voltage range operation while the low-voltage transistor stabilizes the output current, effectively changing the electrical parameters to maintain current stability across varying supply voltages.
Solution Approach 2:
The patent uses a composite transistor structure formed by connecting a high-voltage transistor and a low-voltage transistor in a specific configuration. This composite structure combines the voltage tolerance of the high-voltage device with the current stability of the low-voltage device, resolving the contradiction between wide voltage adaptability and output current stability.
2Power
If the output current of the buffer circuit increases to provide sufficient driving power, then the driving capability improves, but the NPN BJT power transistor becomes over driven and propagation delay increases
Solution Approach 1:
The patent carefully controls the output current parameters through the composite transistor configuration. By adjusting the biasing and transistor sizing, the circuit provides sufficient driving power to switch the BJT quickly while preventing excessive base current that would cause over-driving and increased storage time, thus optimizing the trade-off between power and time.
3Stability of the object's composition
If a long channel transistor or Cascode configuration is used to reduce output current variation, then the current stability improves, but the IC area increases significantly
Solution Approach 1:
Instead of using a single long-channel transistor or Cascode configuration that would consume excessive area, the patent creates a composite transistor by connecting a high-voltage transistor and a low-voltage transistor. This composite structure achieves the current stability equivalent to long-channel devices while occupying significantly less IC area, as it utilizes standard-sized transistors in a clever configuration.
4Stability of the object's composition
If a current mirror in Cascode configuration is used to stabilize current, then the current regulation improves, but additional biasing circuitry is required
Solution Approach 1:
The patent integrates the biasing function directly into the composite transistor structure itself. The connection between the high-voltage and low-voltage transistors inherently provides the necessary biasing without requiring separate external biasing circuitry, thus achieving current regulation while minimizing device complexity.
Data Source
AI summary
A buffer circuit receives a working supply voltage which may vary within a voltage range. The buffer circuit has a high voltage constant current buffer circuit, and in this circuit, the source of the first NMOS transistor is grounded, and drains of the first NMOS transistor and the first PMOS transistor are connected. The source of the second PMOS transistor is connected to the supply voltage input of the buffer circuit, and the drain of the second PMOS transistor is connected to the source of the first PMOS transistor. The input end of the high voltage diode connected composite transistors is connected to the supply voltage input of the buffer circuit, and the output end of the diode connected transistors is connected to the gates of first and second PMOS transistors. The first PMOS and NMOS transistors are high-voltage transistors. The second PMOS transistor is a low-voltage transistor.